CDCM1802: CDCM1802 LVCMOS18 IN/OUT AC/DC SPEC

ALEX jack

Part Number: CDCM1802

Tool/software:

HI TI

We are designing a clk divider solution , Detailed requirment is to divide LVCMOS18 76.8MHZ (single input)refclk into LVCMOS18 38.4MHZ (low additive jitter <500fs ）(single output) ;

Whether LVCMOS18 can be used as a clock input ？ what is the AC/DC spec when LVCMOS as clk input source ?

thanks much~

2 months ago

0 Michael Srinivasan 2 months ago

TI__Expert 3570 points

Hi Alex,

We do not provide AC/DC specs for when LVCMOS is used as a clock input source; however, you can configure the CDCM1802 to accept an LVCMOS by inputting the LVCMOS signal into the non-inverted input pin and biasing the other input pin to the common mode voltage. The easiest way to do that would be to pull the pin up to VDD and down to GND with equivalent resistors (additionally adding a decoupling capacitor to GND, in parallel with the pull-down resistor).

Thanks,

Michael

0 ALEX jack 2 months ago in reply to Michael Srinivasan

Prodigy 80 points

Hi Michael

as shown above ，Use CDCM1802 to change the 76.8MHZ LVCMO18 clock to a 38.4MHZ LVCMOS18 clock

(1) input clk is LVCMOS18 , Vpp=1.8V ， Bias voltage bia VBB supply

(2) output clk is LVCMO18 ， Vpp=1.8V too

There are a few questions to ask ：

（1）Is there any problem with the block diagram of the above scheme ？

（2）What is the VIL and VIH range when using LVCMOS input ？

0 Kadeem Samuel 2 months ago in reply to ALEX jack

TI__Mastermind 18160 points

Hello,

The team is out of office for the holiday weekend. Please expect a response on Monday.

Thanks,

Kadeem

0 ALEX jack 2 months ago in reply to Kadeem Samuel

Prodigy 80 points

HI TI

OK,Thanks for TI's reply and help.

0 Michael Srinivasan 2 months ago in reply to ALEX jack

TI__Expert 3570 points

Hi Alex,

1) Your schematic looks good.

2) The VIL and VIH range will be roughly equal to the common mode voltage -/+ the minimum and maximum input swing, respectively. Therefore, the VIL will approximately range from VDD/2 - 1.3 V to VDD/2 - 0.5 V, and the VIH range will range from VDD/2 + 0.5 V to VDD/2 + 1.3 V.

Thanks,

Michael

0 ALEX jack 2 months ago in reply to Michael Srinivasan

Prodigy 80 points

Hi Michael

If using VBB（VBB=3.3-1.3=2V） provide bias voltage ，LVCMOS18 CLK min voltage is 2-0.9=1.1V，and VIL threshold=VDD/2-0.5=3.3/2-0.5=1.15 ,The voltage margin is relatively low ，I would like to optimize the schematic as follows : CLK min voltage=1.65-0.9=0.75V

（1）Is there any problem with the above scheme ？

（2）Can the VBB 、Y0、/Y0 signal PIN be left floating?

thanks very much ~

0 Michael Srinivasan 2 months ago in reply to ALEX jack

TI__Expert 3570 points

Hi Alex,

(1) I see no issue with the schematic above.

(2) Yes, VBB, Y0, and /Y0 may be left floating if unused.

Thanks,

Michae;

Clock & timing

Clock & timing forum

CDCM1802: CDCM1802 LVCMOS18 IN/OUT AC/DC SPEC