LMK04101: PLL1 of the clock generator is not locking

Hello,

Have you connected a VCXO operating at 10 MHz to CPout1? And have you then routed its output to OSCin? That will be the only way to achieve lock with PLL1. PLL2 is locking because it is connected to the on-board VCO.

Thanks,

Michael

Hi Michael, 
yeah an external VCXO is connected to CPout1 and routed to OSCin. Please check the design for better clarification

Hello again, 

How are you monitoring the lock status of PLL1?

Additionally, would you be able to provide a full schematic for the LMK04101? And could you provide the configuration file of your LMK04101, either as a .tcs file or a hex file (.txt).

Thanks,

Michael

Hi again,

I have done some more research and have found that PLL1 is not locking due to how narrow its frequency band is. It will not indicate that it is locking, but it will behave practically the same as if it were locked. Are your clock outputs as expected?

Thanks,

Michael

Hi Micheal,

We have observed that the device is able to give a stable clock but the frequency is not exactly as we have configured it.

Eg: Expected Frequency is 30 MHz measured output is 30.8 MHz. 

This will also change on power cycles as well.

We did try increasing the BW to 17 KHz but did not see any improvement.

Register Map,

Hi again,

I will get to you soon.

Thanks,

Michael