Other Parts Discussed in Thread: LMK04832, LMK04832-SP
Tool/software:
My customer is planning on using the LMX2615-SP to clock high speed data converters on a space project. He needs to clock the ADC at 11.520 GHz and here is the ADC clock input specs. Customer is trying to meet the listed 28 fs rms jitter spec.
Spec note (1): Intrinsic jitter integrated from 1 Hz to 29 GHz.
Question - This spec is listed as intrinsic jitter. I'm not sure the customer is reading this spec correctly. Is this really the jitter requirement for the input clock or does this represent the additive jitter of the ADC?
Assuming they really need to have a clock with 28 fs rms jitter, Here is a snapshot of their PLLatimum noise simulation with a 10 MHz noise free reference clock and RMS jitter exceeds ADC requirement:
Customer is asking if there are PLL settings that will improve jitter. I told them to increase Fref, preferably to 200 MHz. They will try this but still want to know what can be done at 10 MHz. Can I get help tweaking PLLatinum results for Fref = 10MHz and 200 MHz to optimize RMS jitter.
Customer also said they are following this TI block from our Space product guide, and have followed this in a previous non-space product.
They are requesting if we have a recommendation for a space-grade VCXO in the 100-166 MHz range to use in with the LMK04832? They used a VCXO from Crystek in the non-space design.
I have suggested that ifd the system has the LMK04832-SP with a VCXO, they can us it to cjitter clean the 10 MHz reference and output the 200 MHz Fref to the LMX2615-SP, but they are still interested in jitter data with 10 MHz and 100 MHz inputs.
