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LMKDB1108: LMKDB1108 Single-Ended input and Reduced Output Voltage Swing

Kevin San Diego
Prodigy 140 points

Part Number: LMKDB1108

Tool/software:

I would like to use the LMKDB1108 as a clock buffer in a non-PCIe application due to its very low power. I have couple questions: 1) Can the LMKDB1108 be driven single-ended from a LVCMOS 3.3V source with a resistive divide used to reduce the amplitude below the 2.0V max? What the negative input need to be held at? What is the common mode voltage range of the clock input? 2) The output differential voltage amplitude is too high for my receiver, and I need to reduce the amplitude by around 1/3. What type of resistive structure at the output is preferred for this - resistors on each leg to ground, additional series resistors, resistor across both legs, or some combination of these? 

  • 0
    TI__Genius 12550 points

    Hi Kevin,

    Expect to hear by the end of the week.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    TI__Genius 12550 points

    Hi Kevin,

    The LMKDB1108 can be driven by an LVCMOS 3.3V source with a resistive divide to keep the amplitude below 2.0V max. The negative input would need to be held at the common mode voltage of the signal being driven in. Apply the same resistive divide to a 3.3V supply, and then apply another resistive divide that brings the voltage to one half of the supply voltage (i.e. if you apply a resistive divide to your input signal such that the signal is now a 1.8V signal, the common mode voltage/voltage that should be applied to the negative pin should be 1.8V/2 = 0.9V). 

    In order to reduce the amplitude of the output signal by 1/3, use another resistive divide on each leg. The divider should feature a resistor in series with a another resistor whose resistance is twice that of the first (i.e. a 100 Ohm resistor followed by a 200 Ohm resistor, with the 200 Ohm resistor connected to GND). 

    Thanks,

    Michael