Hello Ron, 

Can you please elaborate on "data sheet doesn't state that. A capacitor on reset (to GND) and a pull up resistor can generate a proper power up reset signal."? where is the risk you see?

If I connect pin 6 to VDD, the output will be driven low and that's not the intended behavior as a latch, right?

Thank you for your support

//Diego

Diego,

Sorry, pin 6 to GND, inactive.

Diego Gil said:

Can you please elaborate on "data sheet doesn't state that. A capacitor on reset (to GND) and a pull up resistor can generate a proper power up reset signal."? where is the risk you see?

On power up [TRIG, THRES, RESET] are all inactive. The output state is "hold". Hold what? There was never any input.

Before power up, a cap is 0V. This makes a low RESET input at power up. This leave nothing to chance or dependency on something that the data sheet doesn't specifically say. 

So you are saying that the initial Output state right after power-up is unknown. But as soon as RESET is high, output should be low as long as TRIG is high, right?

Diego,

Yes. 

Understood now. This will be the ultimate design:

Hello Ron, 

Just wanted to state that your design input resolved a potential problem: right after start-up, output is high when reset is not properly initialized (directly connected to 12V). Increasing the cap connected to RESET seems to solve the problem. 

I still don't understand why you made the following statement then: "The 555 timer does power up as output low". Reality didn't prove so as you predicted.

Also, it seems this is something that should be added in the datasheet.

Thank you, 

Diego

Diego,

How fast was the rise time? 

We first tested with 10nF and 10kohm as shown in the picture above. This resulted in a rise time of 500us and output latched high from beginning.

Second test we did with a 1uF instead. Rise time was around 50ms and output initialized to low as intended. 

I will populate this RC circuit to all reset pins of TLC555 (we have 3 in the design). We can't risk a proper start-up

Diego,

Sorry, I wasn't specific enough. "How fast was the VDD, pin 8, rise time"?   In my experience, the output starts low, but I do not have proof that all samples treated in all ways would do the same. That's why RESET on power up should be used.