Tool/software:

HI ti
The CDCE6214Q1TM clock generator is used to provide one differential clock and one single-ended clock for FPGA,clk input is 50MHz via the SECREF_P
1,Is the design of the circuit shown in the diagram correct?
2,When i write the register via the I2C bus,but CDCE6214Q1TI address(0x68) is no ack ,where is the problem, how can i debug?
ooking forward to your reply,tks!





