CDCE6214Q1TM: LVDS Clock distribution and buffer requirement

Hello,

1. In general, differential clock signals will perform better than single-ended. It can be okay to use single-ended depending on the performance of the clock generator, but it is highly recommended to route the traces as a differential pair to mimic differential clock signal performance. (See page 2 of this app note: https://www.ti.com/lit/an/snaa408/snaa408.pdf)

2. How many loads do you intend on driving? Our CDC6C oscillator is capable of driving multiple loads with a single clock, but for anything else we would recommend buffering.

3. You will likely need a buffer, but TI does not have an LVDS to CMOS converter in our portfolio.

4. Sure, depending on the amount of clocks needed, the LMK00334 may be suitable. 

As for the actual clock generator, I have some questions:

- How many loads are you trying to drive with the 2.048 MHz and the 2-8 MHz clock?

- Will the 2-8 MHz clock be a fixed frequency chosen at a later date? Or will this clock frequency need to change while in the application?

- Do you need the full 2-8 MHz range? Some of our clock generators have a minimum output frequency of 2.5 MHz.

- Do the receivers require an LVDS or LVCMOS input clock?

Best,

Cris

Hi Cris,

The clock generator would be placed either on the one Module or the backplane/carrier board and would be going to each module which can have 1 MCU (2-8MHz) with 4 ADCs (2.048MHz), both are single ended clock inputs. The frequency of ADC IC is fixed at 2.048MHz and the MCU frequency would be fixed in the range of 2 to 8MHz.

Since all are single ended inputs, I have to convert the differential clock to single ended using the LVDS receivers. There would be 4 to 5 modules hence 4 to 5 receivers considering 2 channel receivers. This can go up to 10 receivers if I am using single channel for 2 clock signals.

I am selecting CDCE6214Q1TM since it can support both single ended and differential clock output as an option.

For the first option, I am planning to use single ended clock with single ended buffers like SN74LVC2G17.

For the second option, I was planning to use LVDS clock source and LVDS to CMOS converters at the clock inputs such as DS90LV018A (1 Channel), SN65LVDS2 (1 Channel) or DS90LV028A (2 Channel) in addition to these do I need an LVDS buffer at the clock generator output?

For the third option, I want to use Single ended output with LVDS Transmitter at the clock source and LVDS receivers at the clock inputs like DS90LV017A (LVDS Driver) to DS90LV018A (LVDS Receiver).

Which of these options would be a better choice and do i need a buffer for the second option?

Thank you

Vinaayaka,

I agree that the CDCE6214-Q1 should be suitable. From bench testings, using a 24.576 MHz xtal reference would be able to generate your desired configuration with the best performance.

If EMI wasn't much of a concern, I would recommend the first option. The third option seems like an excessive amount of components. 

For the second option, I put together together a proposal with my current understanding of the system. Can you please look it over and make any adjustments needed? I can make the necessary changes to the proposal then.

Best,

Cris

Hi Cris,

My Clock tree design aligns with the block diagram which you have shared, but to reduce the number of components and size, I'm planning to use 2 DS90LV018A in the LVDS to CMOS converter block for MCU and 4 ADC which would be ADS1299. and for the LVDS buffer block, I'm planning to use 2 DS90LV001 buffer for both clock signals.

Is there any issue with driving 4 ADS using single LVDS receiver and how many ADS can I drive at max with out any problem?

Vinaayaka,

Understood. Thank you for updating the block diagram. I am not familiar with the DS9x product line so I am looping in someone else who may be able to answer your questions.

Best,

Cris

Great! Thank you for the information. I'll try out this method and will get back to you if i have any query.

Hey Parker, Sorry I missed to ask a query. How many receivers can a DS90LV001 buffer drive? In case If I am adding more modules how does it affect the signal from the buffer? 

I would also request Cris to rename the shared file or remove it

Thank you

Vinaayaka,

I've removed the file.

Best,

Cris

Hey Parker,

Can you respond to Vinaayaka's additional question?

Best,

Cris

Hi Parker,

If the modules are placed on the backplane such that all the modules branch out on the LVDS lines running straight on the backplane which is terminated at the end like in the below image where the green section would be modules and red would be backplane, will that be okay or do I need to daisy chain?. Will it not add more module to module skew?

Hi Vinaayaka,

Daisy chaining will allow the shortest possible stub lengths for the unterminated stubs. You can use the above layout if your stubs are short enough. The propagation delay of the stubs should be < 30% of the minimum differential transition time of the device to be okay - but the shorter the better. If you don't - the higher frequency content of the signal will see the unterminated stub as a parallel transmission line - which is what you want to avoid. 

For this device the minimum listed transition time is the fall time which has a smallest listed value of 225ps - so ideally the propagation delay of the stub needs to be <67.5ps - that is why I originally suggested daisy chaining - but that may not be possible in your system. 

Best,

Parker Dodson