LMK1C1102: Best option for flexible input stage to a wave period analysis circuit

Hi Simon,

For the single-ended +/- 1V sine wave (2 Vpp if I understand you correctly), the most appropriate way to treat the input would be to AC couple and then rebias it to a midpoint voltage of VDD/2. That way, the VIH and VIL specifications are satisfied.

For the strobe input, I would actually recommend a similar part - the LMK1C110xA (https://www.ti.com/product/LMK1C1106A). It is an asynchronous part, designed specifically to be able to handle low frequency/irregular inputs, such as a 1PPS input. Given the swing of that signal, no input circuitry will be required.

Thanks,

Michael

Hi Michael, thank you very much for your advice! I'm especially grateful that you pointed out the suitability of the LMK1C110xA parts.

To AC couple the input with a series capacitor and bias voltage, I have a couple of outstanding questions:

1. What would be a recommended way of switching that "AC-coupling & bias" front end out and connecting the CLKIN pin directly to my strobe pulse input? Is there a recommended approach with analog switch etc? I need the same input to handle both signal types, albeit with some reconfiguration allowed. I also need to maintain the pulse duration on the output of the part, so can't keep the input AC coupled for the strobe pulse input.
2. Do you think the AC-coupling capacitor will significantly affect the representation of the zero crossing time on the output? There isn't a significant smoothing effect?

Hi Simon,

Simon Merrett said:

What would be a recommended way of switching that "AC-coupling & bias" front end out and connecting the CLKIN pin directly to my strobe pulse input? Is there a recommended approach with analog switch etc? I need the same input to handle both signal types, albeit with some reconfiguration allowed. I also need to maintain the pulse duration on the output of the part, so can't keep the input AC coupled for the strobe pulse input

I would recommend using a SPDT switch that allows you to switch between the two inputs using logic. I have attached resources below (including an old E2E with some suggested part numbers)

Analog Switches and Muxes: https://www.ti.com/switches-multiplexers/analog/products.html#p1143=2:1%20SPDT&sort=p3306;asc

Old E2E: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1187353/lmk1c1104-spdt-switch-recommendation-for-the-clk-input/4480434#4480434 

Simon Merrett said:

Do you think the AC-coupling capacitor will significantly affect the representation of the zero crossing time on the output? There isn't a significant smoothing effect?

The AC-coupling capacitor will bring the crossing point (midpoint, considering it is single-ended) of the input signal down to GND. With the re-biasing, the outcome is that the swing will have the appropriate offset to satisfy the requirements of the receiver, so that the low and high signals will be interpreted correctly. The AC coupling capacitor should have no impact on the zero crossing time on the output - so long as it is used correctly.

Thanks,

Michael

Thanks Michael. I need to use the same coaxial input connector for both signal types. I extended the SPDT scheme you suggested (and I had considered but wanted comment) to make this work. I have used basic SPDT switch symbols to represent where an analog switch would perform a circuit function because I don't have a part yet selected:

This leaves me with implementation questions about SW1, as it needs to handle negative voltages for the sine input signal. I believe I could use a dual supply analog switch, and create a negative rail with something like LM27762 to generate a low noise negative rail. Or, I could use a single supply analog switch (perhaps with better bandwidth performance than a dual supply switch, especially as I have to cascade two in series) and create a floating supply for it with the LM27762. For example, the LM27762 could create a -1.6V rail to connect the analog switch ground rail to, and a 3.3V rail to connect its VDD pin to. I might also connect the VDD of the LMK1C1102ADQF to this rail, as I am considering a separate low noise supply for that part anyway.

Please could you comment on these two approaches, whether there is a better way to tackle this aspect of the design and, especially given the cascaded switches and need to handle -1V on one input, whether there would be any change to the switch parts recommended.

Hi Simon,

I am going to refer this question to the relevant people from switching support to assist with these questions.

Thanks,

Michael

Hi Nir,

Yes I do want to handle 3.3V and -1 V (I suggested -1.6V because that gives a 5V range which is suitable for some parts). Looking at your kind suggestion, it seems like an older part and I am concerned about propagation delay of my signals of interest through it. It appears to have a 180 MHz bandwidth which appears to me to be a bit close to the recommended 1.5 x sine frequency (https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1187353/lmk1c1104-spdt-switch-recommendation-for-the-clk-input/4480434#4480434) when my frequency is up to 100 MHz and I will need to cascade two connections in series to achieve my goal (I think). Based on https://www.ti.com/lit/an/scda047/scda047.pdf? it looks like I will halve my multiplexer's -3dB bandwidth further. 

So,

• Is there a scheme to use the CD74HC4053 to achieve my circuit above without needing to cascade, or
• Can you recommend a part suitable for 100 MHz sine clock and 2 switches cascaded, or
• Can you explain why CD74HC4053 is actually still suitable based on the cascaded use and 180 MHz bandwidth

I'm not experienced in selecting these types of parts, so I may have focussed on the wrong areas of the specification or misunderstood how to best employ such a part for my needs. Thanks again

Hello Simon,

The CD74HC4053 is a 3-channel 2:1 so I don't think you need to cascade. You can combine a couple of the channels as below:

Here is the propagation delay information for the CD74HC4053, is it fast enough?

Thanks,

Nir 

Hello Simon,

So to make sure I understand your request, you are looking for a SPDT that can handle 3.3V and -1.6V signaling?

If that is the case, then I can recommend the CD74HC4053.

Thanks,

Nir 

Hi Nir, thanks. I think I need to clarify a few things:

1. Your pins seem to have the numbering of 1 and 3 are the "channel IN/OUT" pins? 2 is "Channel common IN/OUT"? 
2. You use the middle channel to accept the incoming wave_in signal, and the top channel to send out the signal to CLKIN (even though the arrow signal is suggesting an input, it is an output)
3. If 1. and 2. are true, is the connecting of output of one channel to another channel not the electrical equivalent of cascading the switches? Does this not have the same effect on bandwidth as described in the TI paper I linked above?
4. I have been led to believe (from another TI representative on these forums) that in the logic switching world, because jitter specs are not published, jitter performance (and I am particularly interested in cycle to cycle jitter) is best inferred from propagation delay timings. I do not have hard limits other than to minimise the cycle to cycle jitter to the CLKIN pin, whether the signal is the AC-coupled biased sine wave or the 1 PPS strobe pulse directly fed through the switches to CLKIN. A target should be under 10 ps but better should be achievable. The LMK1C1102ADQF has excellent jitter, propagation and rise time specs and I am concerned an older process part like the CD74HC4053 with propagation delay in the order of 30 nanoseconds by the time I have connected two mux channels together will allow for far too much jitter. This is part of the OP question I have above, about whether a better approach is to use an ultrafast comparator instead of a clock buffer. If we cannot condition both signals into the clock buffer in a very (timing) stable way, is the comparator approach better because there is no need to put an analogue switch directly on the signal path of the comparator input? I hope to find a very time-stable (minimal variation in propagation time / cycle to cycle jitter) analogue switch to allow this clock buffer approach to work, as I very much like the LMK1C1102ADQF specs.

Hello Simon,

Our multiplexers are passive and analog. So they are bidirectional and can pass analog and digital signals. The CD74HC4053 is a 3-channel 2:1, so it can behave like 1 input and 2 outputs, or 2 inputs and 1 output mux across the three channels. 
The numbering I followed from the diagram you provided. 

Cascading is when a signal is passed through two or more multiplexers in series. Here I am just shorting the channels together, it will not degrade the bandwidth. 

Yes, jitter is not a spec we specify for our parts. The only thing we do is propagation delay, which is basically just the RC of the mux. 
Unfortunately I don't believe we have a mux that can meet the additional prop delay requirements. 

I am not an expert on comparators, so I am not really sure what is the best option here. 

Would you prefer for me to loop in the comparator team to help provide the best option?

Thanks,

Nir 

Hi Nir, thanks for clarifying. So even though this would require two channels and the signal would pass through both of them, it is not considered cascading in the same way that the article discusses? 

I am happy to take your advice on this, regarding the negligible impact on bandwidth.

I misunderstood your description of propagation delay. If there is no measurable delay between the signal input on a CHANNEL IN/OUT pin and CHANNEL COM OUT/IN if they are shorted, then I am happy. I was not asking about the time between a change of logic applied to !E or Sel pins having an effect on the output.

On the alternative multiplexers, TMUX4053 looks OK - is it worse than CD74HC4053 in some way? I can see higher Ron but not much else is a problem and is a higher bandwidth, which might be good for my application? Is it forbidden to operate a TMUX1072 with its ground pin connected to a -1.6V rail and VCC to 3.3V? I can use pulldown resistors on logic inputs like SEL and OE, pulling up to 3.3V for high logic levels.  Signals won't exceed the potential at either power pin. TMUX1072 seems to have very low Ron so will make my termination simpler. If this negative rail approach is acceptable, what other parts might be better suited?

I would appreciate input from comparator experts on their opinion of the options I have. I think I would still need to generate a negative rail for that approach anyway.

Hello Simon,

If the signals will passing this way, then yes this is technically cascading since it is passing through two switches and will degrade the bandwidth. 

Here is an FAQ explaining how we define propagation delay, it should be able to explain it better. 

The TMUX4053 is better spec wise than the CD74HC4053, but it wasn't able to meet your prop delay requirements so I didn't recommend it.
You can implement it instead, and since the bandwidth is much higher it should resolve the cascading problem.  

I am not sure if the TMUX1072 will work this way since its supply requirement is minimum 2.3V. If you are ground shifting by -1.6V then VCC will have to be at least 3.9V.

Ok, I will loop in the comparator team to this thread.

Thanks,

Nir 

Hi Nir, that is a very useful FAQ for me, thank you. So if I use the input load capacitance of the LMK1C110xA parts, 7 pF typical, and the internal pulldown resistor of 300 kΩ (negligible) and biasing resistors (100 Ω each) , I can calculate my propagation times through these analog switches and the rest of the network. 

If I use the approach in their example with the propagation delay of 4 ns (for +/- 5V) cited in the datasheet for TMUX4053, the load capacitance and resistance seems to be needed and I don't see these quantified in 6.7 Timing Characteristics table against prop delay. If we assume the 50 pF and 10 kΩ mentioned in other timing tests, I calculate using per channel on resistance of 60 Ω and C(ON) = CS(ON) + CD(ON) = 20 pF from 6.6 AC Characteristics, that R*C = 60 *(50 + 20) = 4200 ps, or 4.2 ns, matching the claim.

If I can float the ground lower, I can select much faster propagation parts. For example TMUX1574 looks like 50 to 95 ps propagation delay, thanks to its low Ron and Con. (6.7 Timing Requirements). Is there any considerations of floating the ground lower, other than meeting the max/recommended operating ratings?

Regarding "TMUX4053 is better spec wise than the CD74HC4053, but it wasn't able to meet your prop delay requirements" but how does the CD74HC4053 outperform it if that was your initial recommendation? Is there a spec in the CD74HC4053 which I have missed as the reason to choose it?

Look forward to comments from the analogue switch and comparator experts. 

Hi Nir, great thanks for further clarification. I misrepresented my target - I think I meant 10 ps of cycle to cycle additive jitter, although I would have accepted RMS jitter as it is not a hard requirement. Propagation can take longer but I need propagation time to be very stable to get near 10 ps additive jitter hence I was looking for the shortest Tprop available. I think a ground shifted TMUX1574 is a good option right now. With two channels connected to the LMK1C1102A, we could have a very fast and hopefully stable combination. 

I would still appreciate comment on the comparator approach, with no need to decouple into the comparator front end. I'm just using propagation delay as a proxy for propagation delay jitter, so some propagation time is acceptable if the timing of the output is a high fidelity representation of the input. I will mark resolved once comparator expert has contributed.

Thanks for your post.  We are on holiday break and will review when we return on Monday.

Chuck

Hi Simon,

Nir is OoO today but please expect a response from him early this week.

Regards,

Kameron

Hope you all enjoyed your break. Would it be possible to get some input from a comparator expert on the alternative approach discussed in the OP please, as offered by Nir, please?

Hi Simon,

I read through the post, but I'm jumping into this a bit late, so please correct me if my understanding is incorrect.

From what I understand, the alternate approach is suggested to remove the need for a decoupling capacitor at the input to the comparator.

The TLV3801 has an input common mode voltage range of VEE + 1.5 to VCC:

This means that with VEE = -1.65V and VCC = 3.3V, the input common mode voltage range is -0.15V to 3.3V. Directly connecting the +/- 1V sine wave to the comparator input would result in an input common mode voltage violation for much of the negative portion of the input sine wave.

You'd have to mitigate this by diode clamping the input similar to this circuit cookbook, or add a DC bias to the sine wave with an input structure like the AC coupling capacitor shown in the original post.

Hi HO,

Thanks for your reply - yes there's quite a lot to go through in this thread. You are correct in heading back to my original post, trying to decide the approach to take. You are also correct in your understanding that I would like to consider a dual supply comparator as a means to remove the need for a series capacitor in the signal path. However, if I were to use a comparator like the TLV3801, I would make VEE = 3.3 V, which I think solves the issue you describe.

My main requested input from you and your expertise is about how well the comparator scheme will preserve the timing of the IN- voltage crossing times for sequential rising edges on the signal, especially given that I need to convert the LVDS input back to CMOS/TTL to interface with other elements of my time stamping circuitry (SN65LVELT23 is my suggestion in the OP but I am happy to be informed of a more suitable part for high time fidelity applications). 

The main datasheet spec I can see which is related to the timing fidelity of an output with respect to the input, is jitter. I have previously understood that low propagation delay can be used as a proxy for additive jitter, especially where jitter is not specified on a part. However I do not explicitly require low propagation time, if the additive jitter of a part is otherwise extremely low.

Hi Simon,

Did you mean VEE = -3.3V relative to GND? For the TLV3801, the VEE cannot be this low as the device power needs to satisfy the VCC - GND > 2.4V condition:

A negative rail of VEE = -3.3V leaves no room for VCC to satisfy the 2.4V minimum without exceeding the VCC - VEE < 5.25V maximum.

To use the TLV3801 for the +/-1V sine wave, you'd need to use VEE = -2.5V and VCC = 2.5V in order for the input common mode voltage range to be -1V to 2.5V and satisfy the device power requirements.

Without a direct jitter specification, you can use the dispersion specifications on the data sheet to get a general idea of how the input to output timing changes with changing input signals:

These specifications vary the overdrive, underdrive, and the common mode of the input signal and measure the typical effects of those on the propagation delay.

Thank you for pointing that out Ho. So I would need to either have

1. Switched voltages to VCC and VEE: 3.3V and -1.5V respectively, for the 3.3V pulse, and 2.5V and -2.5V for the +/- 1V sine wave, with IN- switched between 1.65 V for pulse or GND for sine, OR,
2. Keep VCC and VEE at +/- 2.5 V and clamp the 3.3V input to +2.5V, with the same switching for IN-

Also, thank you for highlighting the drive variance contribution to propagation delay. Is it correct to interpret those value being stable if the voltage of the waveform is stable at a given phase angle?

Thanks Ho!