Hi all,
I am working with two of the ZCU 216 with the clk 104 add-on card. I have 10 MHz and 1 pps input, and they are very stable (From Brandywine GPS clock). But i have an issue when i do a power cycle, the phase between 2 FPGAs doesn't match. I believe the root cause isthe LMK04828 CLK file. There are multiple parameters in the TICS clock file. I don't know which parameters I should use to sync them. As of now, I am testing 10 MHZ output from the CLK 104 add-on card using an Oscilloscope. I am attaching the TICS file for reference.
I am trying to get an output of 200 MHz from output from LMK04828B.LMK04828B_B3000M_200M_MTS_SYSREF_5M_Clk0_dis_dync_20230316.txt
I have read a similar issue
Thank you
Best
Sharma Bishnu