LMK04828: LMK04828: ZCU 216 board phase doesn't align after power cycle.

Part Number: LMK04828


Hi all, 
I am working with two of the ZCU 216 with the clk 104 add-on card. I have 10 MHz and 1 pps input, and they are very stable (From Brandywine GPS clock). But i have an issue when i do a power cycle, the phase between 2 FPGAs doesn't match. I believe the root cause isthe  LMK04828 CLK file. There are multiple parameters in the TICS clock file. I don't know which parameters I should use to sync them. As of now, I am testing 10 MHZ output from the CLK 104 add-on card using an Oscilloscope. I am attaching the TICS file for reference. 
I am trying to get an output of 200 MHz from output from LMK04828B.LMK04828B_B3000M_200M_MTS_SYSREF_5M_Clk0_dis_dync_20230316.txt 
I have read a similar issue 

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1347551/lmk04828-generating-a-phase-aligned-10mhz-output-clock

Thank you 
Best
Sharma Bishnu

  • Hi Sharma,

    Are you re-synchronizing the outputs upon each power cycle? You have all of your SYNC_DISX bits set, which would explain why - even if you attempted to synchronize the outputs - the output phases change between power up cycles. Can you try setting those all to 0? And setting the SYNC_1SHOT_EN bit to 1? This is important for your ZDM feedback output, and ensuring that it does not stay in a reset state during the triggering of a SYNC event.

    Furthermore, can you share your VCO frequency? I believe your file loaded into my TICS Pro incorrectly, but I am seeing a frequency of 187.5MHz, which is well outside of the band that VCO1 can support.

    Thanks,

    Michael

  • The VCO frequency is 160, and the output frequency is 200 MHz. As of now, I have designed a working file, it looks promising. Sin_enable is ON, and other parameters is off. I think the main thing to keep in mind is how the N and R divider works when we try to sync them.