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LMK04828: HSDS output common mode level

Markus Sporer
Prodigy 30 points
Part Number: LMK04828
Other Parts Discussed in Thread: AFE7900, AFE7900EVM

Dear TI team,

I am currently working with the LMK04828 to supply clock signals to the AFE7900. I have a few questions regarding the common mode level of the HSDS output.

In my setup, all clocks from the LMK are AC coupled, except for the SYSREF. The AFE7900 requires a common mode level of approximately 700mV for a DC-coupled SYSREF, along with a differential swing of 600mVpp. On the AFE7900 evaluation board (AFE7900EVM), the LMK04828 utilizes a 6mA HSDS output combined with a voltage divider to achieve a suitable common mode level while maintaining sufficient swing. I measured a common mode level of around 700mV on the evaluation board, which aligns with the requirements of the AFE7900.

However, when I refer to the LMK04828 datasheet, I find it unclear where this common mode level originates. The datasheet does not specify a common mode level; it only provides high and low levels, which suggest a calculated common mode level of approximately 1.9V. Considering the voltage divider on the AFE7900EVM, I would expect a common mode level of around 950mV, which contradicts my measurements and could potentially overload the AFE7900. Could you please clarify the common mode level for the HSDS output options of the LMK04828? 

Best,

Markus

  • 0
    TI__Genius 12240 points

    Hi Markus,

    This is a good question. I will be able to confirm in lab tomorrow.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 30 points

    Hi Michael,

    Thanks for your reply. Could you already do the measurements? 

    Thanks and best,
    Markus

  • 0 in reply to Markus Sporer
    TI__Genius 12240 points

    Hi Markus,

    Sorry for the delay. I tested this on bench using the LMK04828EVM. I probed before the AC coupling capacitors on the evm and found the common mode voltage to be ~1.2V.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 30 points

    Hi Michael,

    thanks for the clarification! Do you also see a mismatch with the LMK datasheet here? The datasheet specifies high and low levels for HSDS which result in a calculated VCM of ~2V (VCM=(VOH+VOL)/2).Am I misinterpreting the provided information, or how can the user determine the correct HSDS common mode level from the datasheet?

    Thanks,
    Markus

  • 0 in reply to Markus Sporer
    TI__Genius 12240 points

    Hi Marcus,

    That is not specified in the datasheet because the typical output structure of an HSDS driver should involve an AC coupling capacitor. Based on the way the datasheet specifies it, I also came to the conclusion that the output common mode voltage should be ~1.95V. However, the datasheet also specifically says that any HSDS output driver needs to be AC coupled.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    TI__Mastermind 34270 points

    There is a feedback loop in the output driver for HSDS that should keep the DC voltage at roughly the same nominal common mode voltage regardless of loading or AC/DC coupling, provided the driver is still in current compliance relative to the load. That said, HSDS was assumed during design to be AC-coupled, obviating the need for any specific common mode requirement; and although there's no particular reason it can't be DC-coupled to a 100Ω differential load, the common mode is highly process-dependent and should not be assumed (by the AFE team or by users) to be a constant value. 1.95V is at best a nominal value, and I'd expect ±200mV in either direction.

    I think you should discuss with the AFE7900 product owners and investigate the stringency of the VCM and swing requirements. Is the VCM requirement really 0.6V to 0.8V? Or is this just where the nominal transition occurs, and an alternate common mode could induce duty cycle distortion or reduced slew rate through the relevant edge transition region?

  • 0 in reply to Derek Payne
    Prodigy 30 points

    Hi Michael,

    Hi Derek,

    Thank you both for your responses. It's good to know that the HSDS output can be DC coupled, as this is a crucial feature for SYSREF. However, I have some concerns regarding the compatibility between the LMK and AFE. I had always understood that the LMK and AFE were a well-matched and preferred solution provided by TI, especially since they work together on the AFE evaluation board with the DC coupled HSDS output serving as SYSREF.

    That said, I’ve understood that there may be a potential mismatch in the common mode for SYSREF. While this might not pose an issue on the evaluation board, I need clarification on this matter before I can confidently integrate the LMK and AFE into our products.

    How should we proceed? Would it be possible to involve someone from the AFE team in this discussion? Thank you!

  • 0 in reply to Markus Sporer
    TI__Mastermind 34270 points

    I've requested someone from AFE team to comment; they will be available after US holiday weekend is over (1st Dec).

  • 0 in reply to Derek Payne
    TI__Expert 8559 points

    Derek, is there an update to this question?

    Best regards

  • 0 in reply to franziskus
    TI__Genius 12240 points

    Hello,

    It appears the team was not added. I will do so now.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    TI__Mastermind 18351 points

    Hi Markus,

    How are you planning to use the AFE and SYSREF? Is this going to be single shot sysref or continuous sysref? To simplify the clocking we typically recommend AC coupling SYSREF and using a continuous SYSREF, which is only on during the AFE configuration and turned off afterwards to avoid any spurs. 

    Otherwise we recommend adding a voltage divider to get the correct common mode to the AFE from the LMK. 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 30 points

    Hi David,

    Thank you for your response and support. We want to have the option for a single-shot SYSREF. From my understanding, if we AC couple the SYSREF and then turn off the continuous SYSREF, the digital AFE input would become a high-impedance node since it would only have the MOS gate and differential termination connected. Or are the digital inputs self-biased?

    Regarding my initial question: I understand that the AFE EVM utilizes a 1:1 voltage divider to attenuate the LMK common mode. However, I is unclear to me on how the LMK common mode remains within the min/max range of 0.6-0.8V (AFE datasheet). Your colleague Derek Payne mentioned that the LMK common mode can vary by +/-200mV due to process variation. This variation alone would result in a +/-100mV change in the common mode seen by the AFE after the voltage divider. This would be acceptable if the LMK common mode (typical value) would be exactly at 1.4V, but this is not clear to me. The LMK datasheet does not specify a common mode for HSDS. The calculated common mode from the high/low levels is 1.95V, while my measurement shows 1.4V, and your colleague Michael Srinivasan measured it at 1.2V.

    I may be misunderstanding the information, despite having read the datasheets carefully, or there could be missing details. I would appreciate any advice on how to connect a DC-coupled SYSREF from the LMK to the AFE without violating the datasheet specifications (AFE SYSREF min/max levels). From my perspective, this is currently not possible since a) the acceptable input common mode range of the AFE SYSREF is small b) the LMK seems to have large variation on the common mode level c) the typical common mode level is unclear for the HSDS output.

    Thanks and Best,
    Markus