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LMX1205: LMX1205 Programming related queries, Differential input voltage swing

Ajithkumar Sundar
Prodigy 20 points
Part Number: LMX1205


Hi, 

Currently we are using LMX1205 as a Clock buffer. Having some queries related to that, 

1) Input sensitivity given as 0 to 10dBm for single ended input, What will be Input voltage swing for the differential input? 

2) does CLK_P & CLK_N Voltage offset biasing network is requirement compulsary for LMX1205?

3) We are trying to generate SYSREF signal in all 4 Ch without generating output clock? Is that create any problem in programming the Device? 

 We are facing some issue like, Register file which was generated through TICS Pro loaded in the device and we are able to readback the register. But output LOGICLK & SYSREF signals are not generated. What could be the problem?

  • 0
    TI__Mastermind 34270 points

    I just noticed you made two posts and included the programming here. I gave some responses.

     LMX1205: CLKIN_P & CLKIN_N Differential input Voltage swing related 

    A few thoughts:

    • The RESET bit is set to 1; any time you write R0 (such as, for instance, at the end of a "write all registers" operation), all register states are reset. This should be set to 0 during normal operation. TICS Pro includes an initial write to R0 which clears the device.
    • The SYSREF_DLY_BYP bit is set. I'm not sure if you want to do this in generator mode, since it bypasses the delay generators, and all SYSREFs just come out of the outputs at whatever the propagation delay of the internal routing allows.

    When I load your configuration, clear the reset bit, clear SYSREF_DLY_BYP, and push Ctrl-L to load all registers, I find that the device produces both LOGICLK and continuous SYSREF output.

  • 0
    Prodigy 20 points

    Hi Derek, 

    Thank you for your response. I will check with the corrections. 

    and some of the registers are mentioned as undisclosed in datasheet. And has recommended data to be written. 

    But in TICS PRO it can be change. Is that affect the output generation in buffer mode? 

  • 0 in reply to Ajithkumar Sundar
    TI__Guru** 112720 points

    Hi There,

    Could you provide the discrepancy you observed?  

  • 0 in reply to Derek Payne
    Prodigy 20 points

    Regarding the biasing 2):  the Datasheet says in 6.3.3: "Based on the device internal architecture, for optimal device performance, a voltage offset between pin CLKIN_P and CLKIN_N required. To create a offset, the CLKIN_P and CLKIN_N pins must be biased using external
    resistors. The bias network circuits should be as below. The recommendated resistor values are R2 = 9.5k, R3 =
    7.5K and make R1 and R4 as do not populate." 

    Is this bias necassary?

  • 0 in reply to Till Max Eckroth
    TI__Guru** 112720 points

    Hi Till,

    I don't think this biasing is a must. 

  • 0 in reply to Noel Fung
    Prodigy 20 points

    Thanks Noel. I also measured around 1.35V Bias on these pins, which supports your suggestion.