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LMX2615-SP: LMX2615 SYNC Usage

Josel Go
Expert 6755 points

Part Number: LMX2615-SP
Other Parts Discussed in Thread: LMK04832

Hi Experts,

I'm using a single LMX2615 in a design, and had a question regarding VCO_PHASE_SYNC.  In my application, the part takes in a 100 MHz reference, uses the x2 input frequency doubler with no PreR or R divider, and generates a VCO output of 10 GHz using an N divider of 50.  Output A is set to output this VCO clock directly (10 GHz, no channel divider), but Output B is set to output 5 GHz (/2 in the channel divider).  In this case, is utilization of VCO_PHASE_SYNC required?  Per page 27 of the datasheet, it seems implied that this would be considered Category 1 with Sync mode required, but is this correct?

Lastly, just to mention again, I'm only using a single LMX2615 device.  However, I do require deterministic latency in this application if that affects the answer.  For that, the output of the LMX2615 in the design provides a clock input to an LMK04832, which then distributes the SYSREF and device clocks.

Attached is the output of the register settings I'm using for quick reference.

LMX2615 HexRegisterValues SPI Readout CS20251211.txt 

Regards,

Carl 

  • 0
    TI__Guru** 113830 points

    Hi Carl,

    Since output B is div/2, there are two different phases between OSCin and output B. As such, we need to enable sync mode (VCO_PHASE_MODE = 1). However, when sync mode is enabled, IncludedDivide is equal to 4, the min. N-divider restriction is violated; numerator becomes non-zero. As a result, the configuration is a Cat.4 sync.

    We need to reduce fpd to 50MHz to resolve the problem. Now it is a Cat.1 sync, both outputs have deterministic latency w.r.t. OSCin.

  • 0
    Prodigy 20 points

    This is very helpful, thanks!  So just to confirm, using the channel divider to /2 for the B output is enough to introduce non-deterministic latency for the B output?  I ask because I'm a little unclear on how a /2 would introduce non-deterministic behavior.  I'm poking at this some because I do care about phase noise at the output, and dividing the input down to 50 MHz results in more phase noise, so just want to make sure I understand before going that route.  Thanks!

  • 0 in reply to Carl Spurgers
    TI__Genius 12550 points

    Hi Carl,

    No, it was the high FPD frequency that resulted in the non-deterministic latency. This resulted in the N divide value being less than the minimum for the restriction that pertains to category 1 SYNC.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    TI__Guru** 113830 points

    Hi Carl,

    Since the frequency of RFoutA is an integer multiple of OSCin, the phases between them are deterministic. There are some propagation delay between input and output, their edges are therefore not exactly aligned, this is normal. As long as the environment is identical, every time you program the device, you should see the same amount of delay. 

    RFoutB is divided down from the VCO (= RFoutA), there are two possible output states, depending on which VCO edge is actually chosen to start dividing. RFoutA and RFoutB are always aligned, as RFoutB is divided down from RFoutA. However, RFoutB is not always aligned with OSCin due to the two possible output states.

  • 0
    Prodigy 20 points

    Perfect, that all makes sense, thanks!