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AM62L: AL62L I2C Clock Waveform to PMIC TPS65214

Part Number: AM62L
Other Parts Discussed in Thread: TPS65214

Hi Support,

Could you please review the attached waveform and confirm whether the shape and duty cycle are acceptable?

The AM62L pins AB22 and AA22 are connected to the PMIC (TPS65214) I²C lines. We have used 4.7 k pull-up resistors on both SCL and SDA.

The SCL frequency is configured at 400 kHz. We are observing that the clock duty cycle is not close to 50%, and the rise time appears longer than expected. We would like to understand whether this behavior could be due to measurement limitations or if it indicates a bus-related issue (pull-up value, bus capacitance, etc.).

As a mitigation, would it be acceptable to operate the I²C bus at 100 kHz for communication with the PMIC to avoid this behavior?

Please find the attached SCL waveform for your reference.

Thanks and regards,
Kunal Barot

 
 

image.png

  • Hi Kunal,

    Thank you for the query !

    According to the AM62L Datasheet, the AM62L I2C Controller is compliant with the Philips I2C-bus specification ver.2.1.

    On one hand, from the Chapter, ELECTRICAL SPECIFICATIONS AND TIMING FOR I/O STAGES AND BUS LINES / Section, Standard- and Fast-mode devices /  Table, Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices of the Philips I2C-bus specification ver.2.1 it can be calculated (based on the minimal T+width_min and T-width_min)  that the DC is ~ 32% in FAST-MODE (400 kHz). 

    DC % = (T+width_min / (T+width_min + T-width_min)) * 100% = (0.854 / (0.854 + 1.7502)) * 100  =  32.79%  ~ 33%

    On the other hand, from the  below table of the Section, I2C Interface of the TPS65214 DS we can calculate that the SCL DC, required at the TPS65214 I2C SCL input, is  approximately 32%. It is compatible with the Philips I2C-bus specification ver.2.1 and therefore the SCL DC is OK.

    Both the AM62L SCL output t_rise_max and TPS65214 expected SCL input t_rise_max- defined in the Philips I2C-Bus Specification ver.2.1 and the TPS65214 datasheet (see below table) respectively correspond to 300 ns:

       

    From the AM62L datasheet I can see that you use WKUP_I2C0_SCL and WKUP_I2C_SDA pins of the AM62L SoC. These use 1P8_LVCMOS buffer type for which the minimal requested slew rate (minimal SCL clock input slew rate) can be expressed as: 9*f [V/s], where f is the signal toggle frequency in Hz. At 400 kHz this means :  SR_min1 = 9*400*10^3 = 3600000=3.6*10^6 V/s, SR_min2 = 1.08*10^5 V/s. According the tablenote 5 under the below table of the Datasheet, the  SR_min = MAX(SR_min1,SR_min2) = 3.6*10^6 V/s.

    Let's consider that the rise time tis the time of an voltage change from 20% to 80% VDD where VDD=VDDS_WKUP=1.8V.

    t_rise_max = ( 0.8-0.2 ) * VDDS_WKUP / SR_min = (0.6 * 1.8) / (3.6*10^6) =   0.3*10^-6 =  300 ns

    So it seems that your measured AM62L SCL t_rise time = 274.29 ns is less than  t_rise_max = 300ns. However I have doubts that you might lack oscilloscope time resolution because of the higher time axis scale (1 uS/div).

    Suggested steps:

    1. As a first step  try to increase the scope time axis (X) resolution. Now it is 1uS / div. Try to more accurately measure the rise time setting it to 50 ns / div.

    2. If you have an embedded 1 MHz square-wave oscillator in your scope, please try to perform a reference measurement with the probe and evaluate the shape.   

    I hope this helps !

    Thanks

    Kind Regards,

    Anastas Yordanov