Part Number: LMX2594
Hello,
The customer requires three pieces of LMX2594 to be synchronized. The working state is decimal locked, which is Category 3.
Under normal configuration frequency, LMX2594 can work normally, but if the register is written to the SYNC configuration as follows, it cannot be locked. Please analyze it in conjunction with the following configuration.
The sync signal indicates timing critical, but specific requirements are unclear. Please provide timing or explanation.
LMX2594 is described as follows:
1. The VCO operates in automatic mode.
2. The schematic diagram of LMX2594 is shown below. SYNC is directly connected to FPGA.
3. The initial configuration of LMX2594 register is shown in the attachment.
LMX2694 Initialization Register Configuration.txt
4. The PLL reference frequency is 100MHz, and the phase detection frequency is 100MHz. eg: REF = Fpdf = 100MHz, fout = 8.25GHz.
The SYNC configuration register written after locking is:
VCO_PHASE_SYNC: R0[14] =1
INPIN_IGNORE: R58[15]=0
MASH_RST_COUNT: =50000
CAL_CLK_DIV: R1[2:0] = 0
SYCN provides a pulse with an unknown timing, unknown delay, and a duration of 10ms.
