• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 22 subscribers
  • Views 190 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04832: LMK04832 related issues

jeno.zhang
Genius 3265 points

Part Number: LMK04832

Hello,

The customer is using the LMK04832 product and would like to know the following information:
1. How to handle the clock input and clock output of LMK04832, including LVDS and LVPECL
2. The voltage levels at both ends of the clock are different. How should we handle it?
3. The level types at both ends of the clock are different. How should we handle it? For example, one end is LVDS and the other end is LVPECL.

Thanks.

  • 0
    TI__Guru** 117360 points

    Hi Jeno,

    You are asking for general differential interface questions, there are many collateral in the web, here are some for your information.

    https://www.ti.com/lit/an/scaa056/scaa056.pdf

    www.ti.com/.../snaa377.pdf

    https://www.ti.com/video/series/precision-labs/ti-precision-labs-LVDS.html

  • 0 in reply to Noel Fung
    Genius 3265 points

    Hi Noel,

    The customer has two questions to consult.
    Question 1: Do the LMK04832 reference clock input ports have built-in terminal resistors?
    Question 2: The reference usage provided in the specification sheet is shown in the following figure. Why is the terminating resistor not connected to the pin end?

  • 0 in reply to jeno.zhang
    TI__Guru** 117360 points

    Hi Jeno,

    CLKin and OSCin has internal bias, so AC-couple is required. One exception is when CLKin is configured as MOS input, then it accepts DC-couple.

    CLKin and OSCin input is high impedance, so external termination is required. 

  • 0 in reply to Noel Fung
    Genius 3265 points

    Hi Noel,

    As shown in the figure below, the customer has the following questions. Please help answer them. Thank you!

    Question 1: Why is 240 Ω pull-down selected for the source end? Shouldn't it be selected between 142~200 Ω?


    Question 2: Why are series capacitors added to both the source and load ends? Isn't it enough to add a series capacitor to one end? Which end is recommended to add a series capacitor to?


    Question 3: Why add a 100 Ω matching resistor between two series capacitors? Do we need to add a 100 Ω terminal matching resistor near the input pin of the load end?

  • 0 in reply to jeno.zhang
    TI__Guru** 117360 points

    Hi Jeno,

    Due to recent E2E problem, all screen shot and attachment are not supported. 

    I assume you are referring to Figure 22, LVPECL reference clock source.

    The pull-down resistor value should come from the LVPECL driver datasheet, driver from different vendors may recommend different resistor value.

    LVPECL signal is usually AC-couple, so there are capacitors on the driver side. LMK04832 CLKin requires AC-couple input, so there are capacitors at CLKin.

    The 100Ω resistor is the load to the LVPECL driver.