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LMK04832: LMK04832 lock issue due to VCXO's harmonics?

BH KIM
Prodigy 165 points

Part Number: LMK04832

We are inputting a 10 MHz reference clock and generating a 128.88 MHz clock using the LMK04832.
A Qtech 122.88 MHz VCXO is connected to the OSCinP pin in a single-ended configuration.

The Qtech 122.88 MHz VCXO exhibits harmonics at approximately -28 dBc, -30 dBc, and -40 dBc at the 1/2, 3/2, and 4/2 frequency, respectively.
(The harmonic amplitudes vary depending on the sine-wave peak at 61.44 MHz.)

Although the frequency of the Qtech 122.88 MHz VCXO is changing in response to the reference 10MHz, the LMK04832 is unable to achieve lock.
Could these harmonics be affecting the locking behavior?

If the harmonics are affecting the operation, what is the maximum allowable harmonic level?

  • 0
    TI__Genius 13751 points

    Hi BH,

    These harmonics should not be causing the loss of lock. Can you provide your register configuration? 

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 165 points

    Hi Michael


    For reference, when we replaced the Qtech device with a Crystek product on our board and tested it, the LMK04832 was able to lock without any issues.
    The register settings are provided below.

    Thank you.

    0000 90
    0000 10
    0002 00
    0003 06
    0004 D1
    0005 63
    0006 50
    000C 51
    000D 04
    0100 13
    0101 0A
    0102 10
    0103 40
    0104 00
    0105 00
    0106 01
    0107 11
    0108 13
    0109 0A
    010A 10
    010B 40
    010C 20
    010D 20
    010E 01
    010F 41
    0110 13
    0111 0A
    0112 10
    0113 40
    0114 10
    0115 00
    0116 01
    0117 11
    0118 13
    0119 0A
    011A 10
    011B 40
    011C 20
    011D 20
    011E 01
    011F 11
    0120 13
    0121 0A
    0122 10
    0123 40
    0124 10
    0125 00
    0126 01
    0127 41
    0128 13
    0129 0A
    012A 10
    012B 40
    012C 10
    012D 00
    012E 01
    012F 11
    0130 13
    0131 0A
    0132 10
    0133 40
    0134 20
    0135 20
    0136 01
    0137 11
    0138 11
    0139 00
    013A 00
    013B 98
    013C 00
    013D 08
    013E 03
    013F 07
    0140 03
    0141 00
    0142 00
    0143 01
    0144 FF
    0145 00
    0146 1A
    0147 1A
    0148 02
    0149 42
    014A 33
    014B 06
    014C 00
    014D 00
    014E C0
    014F 7F
    0150 01
    0151 02
    0152 00
    0153 00
    0154 7D
    0155 00
    0156 7D
    0157 00
    0158 96
    0159 06
    015A 00
    015B D4
    015C 20
    015D 00
    015E 1E
    015F 0B
    0160 00
    0161 0F
    0162 8C
    0163 00
    0164 00
    0165 0C
    0169 58
    016A 20
    016B 00
    016C 00
    016D 00
    016E 13
    0173 10
    0177 00
    0182 00
    0183 00
    0166 00
    0167 00
    0168 4C
    0555 00

  • 0 in reply to BH KIM
    TI__Genius 13751 points

    Hi BH,

    Can you provide more information on your Qtech VCXO? Given that your configuration locks with the Crystek VCXO, it seems like it may be linked to the Qtech harmonic levels.

    BH KIM said:
    The Qtech 122.88 MHz VCXO exhibits harmonics at approximately -28 dBc, -30 dBc, and -40 dBc at the 1/2, 3/2, and 4/2 frequency, respectively.

    The 1/2 and 3/2 harmonics seem particularly high, especially for what those offsets should be. A maximum allowable harmonic level was not specified for this device. 

    Can you also provide your register configuration as a .txt or .tcs file?

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 165 points

    Hi Michael

    The register configuration is the same for both the Crystek and Q-Tech devices.
    According to the Q-Tech datasheet, the maximum level for harmonics and sub-harmonics is specified as −20 dBc.

    Thank you.

  • 0 in reply to BH KIM
    TI__Genius 13751 points

    Hi BH,

    Is PLL2 the one having the locking issue?

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 165 points

    Hi Michael

    No It is PLL1 Locking Issue

    PLL2 Lock is good.

    Sorry, above TICS pro capture figure is not correct.

    I reattached below figure.

    Additional figure is the VCXO output. As you know, Peak level of sine wave is different due to the 1/2 frequency.

    Thank you.

  • 0 in reply to BH KIM
    TI__Genius 13751 points

    Hi BH,

    Interesting - it seems that the issue may lie in the configuration of your first loop. The PFD frequency introduces a phase noise penalty that could be the issue - when paired with the high harmonics from the VCXO. 

    Could you try a higher CP1 setting? Instead of 450uA, could you try 1050uA?

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 165 points

    Hi Michael

    We had already tried changing PLL1_CP_GAIN. It makes nothing change.

    As you know, Currently, the 10 MHz reference is divided by the PLL1 R divider (R = 125) to 0.08 MHz, and the Q-Tech VCXO is divided by N = 1536, resulting in a 0.08 MHz PFD frequency at PLL1.

    Phase Detector Frequency is quite low.

    Just for test. We changed the reference 10MHz to 10.24MHz. So we can change Phase Detector Frequency from 0.08MHz to 10.24MHz(10.24 is 1/12 of 122.88).

    The test result shows that Lock detection signal is enabled. Unfortunately, we cannot change the reference frequency.

     

    I believe that significant sine-wave distortion due to harmonics can introduce excessive phase error, which may exceed the PLL1_WND_SIZE (maximum 43 ns), particularly when operating with a low phase detector frequency.

    What do you think about this?

    Thank you.

  • 0 in reply to BH KIM
    TI__Guru** 116900 points

    Hi BH,

    When the reference is 10.24MHz, can you verify if PLL1 lock with 1.024MHz fpd?

    is the Qtech VCXO datasheet available online? I am particularly interested to know the input impedance of the Vtune or Vcont pin. 

  • 0 in reply to Noel Fung
    Prodigy 165 points

    Hi Noel Fung

    Actually we did test when the R Divider values are 1(10.24MHz fdb), 4, 6(1.7MHz fpd), 8(1.28MHz fpd), etc.

    PLL1 is locked with 1.706666667 MHz fpd.

    But PLL1 is not locked with 1.28MHz fpd or less fpd.

    You may not find the Qtech VCXO datasheet.

    In the datasheet that I have, there is no information about input impedance of the Vtune or Vcont pin.

    Thank you.

  • 0 in reply to BH KIM
    TI__Guru** 116900 points

    Hi BH,

    My guess the problem is due to a combination of low fpd and low Vtune impedance. 

    Please check with Qtech the input impedance, Crystek input impedance is 51kΩ. If the impedance is low, the current from charge pump will leakage to ground through the Vtune pin and causing modulation or unlock. Increasing fpd can "recharge" the loop filter more often and therefore compensate the leakage.