LMK04832: LMK04832 Setup for HSDS-8mA

Thanks. I understand HSDS is a current-mode output and needs a DC current path. My questions are specifically about the required/common-mode bias for HSDS-8mA on LMK04832:

1. With no external bias rail provided (i.e., no “50 Ω to VCC–1.64 V”), does LMK04832 establish an internal DC bias/common-mode on the HSDS pins so the 8 mA current-mode output operates correctly?  If so, what voltage is established and is it guaranteed to provide full functionality over process and temperature variation?

2. What is the guaranteed compliance / valid output-voltage range (or acceptable external bias range) over which HSDS-8mA maintains its specified swing into a 100 Ω differential load? The datasheet only gives VOH/VOL/VOD under the “50 Ω to VCC–1.64 V” termination condition and does not state a compliance range.

Related: the LMK04832 EVM appears to use HSDS outputs without an explicit VCC–1.64 V termination rail. Unless a DC operating condition is established inside the chip (analogous to the ~1.25 V internal bias in LVDS mode), this seems inconsistent with how current-source outputs operate (they require a defined DC operating point and have a finite compliance range dependent on design and supply).

Thanks,
Farron

Thanks. I understand HSDS is a current-mode output and needs a DC current path. My questions are specifically about the required/common-mode bias for HSDS-8mA on LMK04832:

1. With no external bias rail provided (i.e., no “50 Ω to VCC–1.64 V”), does LMK04832 establish an internal DC bias/common-mode on the HSDS pins so the 8 mA current-mode output operates correctly?  If so, what voltage is established and is it guaranteed to provide full functionality over process and temperature variation?

2. What is the guaranteed compliance / valid output-voltage range (or acceptable external bias range) over which HSDS-8mA maintains its specified swing into a 100 Ω differential load? The datasheet only gives VOH/VOL/VOD under the “50 Ω to VCC–1.64 V” termination condition and does not state a compliance range.

Related: the LMK04832 EVM appears to use HSDS outputs without an explicit VCC–1.64 V termination rail. Unless a DC operating condition is established inside the chip (analogous to the ~1.25 V internal bias in LVDS mode), this seems inconsistent with how current-source outputs operate (they require a defined DC operating point and have a finite compliance range dependent on design and supply).

Thanks,
Farron

Thanks. I don’t think we have a clear answer yet to the core question, so could you please route this to the LMK04832 datasheet owner / clock-output circuit designer / apps manager who can answer authoritatively?

Core question (needs a yes/no):
In HSDS-8mA mode, does LMK04832 provide an internal DC common-mode / bias (i.e., an internal operating point for the current-mode output stage), or does HSDS require an external bias termination rail (as implied by the datasheet condition “50 Ω to VCC–1.64 V”) to establish its DC operating point and meet the datasheet levels over PVT?

Two points I’d like clarified/corrected as part of that answer:

1. “HSDS is intended for AC-coupling, Vcm is not important at all.”
   Even with AC coupling, the output stage still requires a defined DC operating point (whether internally or externally established) to remain in its valid operating region and produce the specified current/swing. So the question is where that DC operating point is established.

2. “There is no compliance range.”
   Understood that HSDS is proprietary and not an industry standard, but the HSDS output stage still has a finite valid output voltage range (compliance) determined by the device design and supplies. Transistor current sources are not ideal and are limited by their supply range and required drop across transistors, so there has to be a compliance range. 

A simple statement of either:

• “HSDS self-biases internally, and the VCC–1.64 V termination is test-fixture only,”
  or

• “HSDS does not self-bias; external termination to VCC–1.64 V (or equivalent) is required for datasheet-guaranteed operation,”
  would resolve this.

Thanks,
Farron

Hello Noel:

 Thanks for looking further, but our own measured data still indicates a possible problem.  Today we measured the DC content on Channel 8 in the EVM kit in HSDS-8, and on this particular unit it is 2.035V.  Swing is 400mVp on one channel, so that peak comes up to 2.435V, which is 0.865V from the positive rail.  We don't know the nature of the high side driver.  If it is cascoded for hi-Z output as is often done in chip design for current sources, this voltage could be quite close to departing the current source mode via saturation.  That’s why you will often see op amp outputs spec’ed to come within about 1V of the rails but not closer. 

 Connecting a 100 ohm resistor between two floating nodes does not provide them a DC condition in the middle of the compliance range.  It is just ensuring that the two nodes are at similar floating voltages, which could be a poorly performing voltage out of the compliance range.   

 The main ways to force current source outputs to be in the middle of their compliance range (usually around mid-supply) or to any desired point in the range is direct DC coupling (like 50 ohms to 1.66V as called out in the datasheet), or by negative feedback compared to another voltage (like in a closed loop op amp).

 Is it not possible for you to tell us if the HSDS outputs have internal DC bias or not? 

 It does seem to be “not” from our measurement of 2.035V DC, which is not a sensible bias voltage.  The question would then become if that kind of variation from a more centered bias is reliable to count on over production.

Thanks,

Farron

Hi Farron,

The HSDS output driver does have an internal nominal bias of 1.95V - I would expect a variation of ±200mV. 

There is a feedback loop in the output driver for HSDS that should keep the DC voltage at roughly the same nominal common mode voltage regardless of loading or AC/DC coupling, provided the driver is still in current compliance relative to the load.

To echo what Noel said, HSDS was assumed during design to be AC coupled, precluding the need for a specific common mode requirement.

Thanks,

Michael

Hello Michael:

Thanks for that key information.  Since you are DC biasing that HSDS driver on purpose at that rather high voltage of 1.95V nominal, it should be safe to assume that the high side driver design works fine with it despite the datasheet condition being 1.66V. 

You are still assuming a resistor between the HSDS pins and then 100 ohms termination on the far end of the lines just before AC coupling into the target.  For the LMK04828 that transmit side resistor was recommended by TI as 560 ohms, though it is not currently stuffed in the LMK04832 EVK board for HSDS-8 operation.   A logical reason for that resistor at the LMK side would be that the feedback loop you are reporting is there likely applies to just one side of the driver, so that the resistor is needed to bias the other side just in case the target provides 100 ohms on its die that is behind AC coupling and thus does not bring the bias for the LMK.  Is that the case?

Related:  The LMK04832 EVK schematic Channel 8 does not have the resistors stuffed for DC connection between the two HSDS driver pins.  Is that accidental?  

Thanks,

Farron

Hello Again Michael and Noe:  Another conflict between data sheet and EVK schemtic is the LVPECL set up.  The datasheet on p.14 notes LVPECL single ended swing from Vcc-2 to Vcc -1 specifically under the condition where the termination is 50 ohms to Vcc-2 = 1.3V.  The EVK schematic has a divider plus resistors to each pin that could allow this.  But instead it is stuffed with 240 ohms per pin going to ground and not a bias voltage.  Why is that?  Thanks, Farron.  

Hi Farron,

I will look this over further and get back to you Monday.

Thanks,

Michael

Hi Michael:

Here is the way the EVK board functions on Clockout 1 in LVPECL mode:

The output swing is 370mV. I am inferring the base voltage.

The datasheet says it should be like below (again base voltage is inferred):

The EVK schematic only delivers 370mV of the specified 1V output swing if the LVPECL output is biased to 1.3V.  So, it is a mystery that the EVK is set up with the 240 ohms to ground instead of the 50 ohms to 1.3V that is called out in the datasheet.  

Thanks, 

Farron

Hi Farron,

As can be seen in the figure above, the datasheet recommendation is AC-coupled LVPECL - where the swing remains the same, but the output signal has no DC bias. The components are not populated on the EVM, but they can be populated with 50Ohms to the VCC12_CG0 bias voltage. 

Thanks,

Michael

Hi Michael:

Thanks, but that set up is not working to spec for us. But, Fig 22 is you show above is not for outputs from the LMK04832, just for inputs.  It is the way the EVK example schematic is set up for CLKout0, but the problems are that it does not work to spec and there is no explanation of why it should. 

I tried to paste a scope picture, but it won't paste right today (that function is intermittent).  But, in LVPECL 2V mode the swing is 660mV per side and a bit distorted.  

Is it expected that the above set up (240 ohms to ground on each output pin, no DC bias) is supposed to meet the datasheet spec of 1Vpp on each differential output?

The reason we are being particular on this is that we have gone to the trouble to design in an external ceramic resonator oscillator (not using the on-die VCO's of the LMK04832) for the best possible jitter performance.  We need it for 16 bit high speed ADC clocks that we are trying to extract the most effective number of bits (ENOB) from.  The noise is so low that the output driver is a significant source of jitter.  The lowest jitter is achieved with LVPECL output.  But, the LVPECL is working so poorly in the above EVK set up (low swing and distortion) that we don't trust it to give us the simulated jitter from PLLatinum Sim.  

If it just is not commonly known around Texas Instruments how to get the LVPECL to perform to datasheet spec, I can go to Dean Banerjee and ask him what set up he used to get the LVPECL noise data he programmed into PLLatinum Sim.   

Thanks, 

Farron

Hi Farron,

I went down to lab to double-check, and on our EVM (when measuring on CLKout1 with LVPECL2Vpp), I measure a single ended swing closer to what I expect - around 800mVpp. Can you share your configuration file so I can double check it on our bench?

Thanks,

Michael 

Hi Michael:

My client designing this part in is across the country from me and I was not in the lab when the data was taken.  They have the demo kit and I assume they used the configuration that TI recommends.  If I had the file I would not be able to upload it, as I cannot figure out the trick to get E2E to upload files.  

I am guessing that the reason my questions seem overly picky is that a lot of customers have designed in the LMK04832 by copying the EVM User Guide schematics, and it seems to "work".  But, almost all those customers are also using the on-die VCO's with jitter of about 400fs.  Just about any driver probably works OK with that even if the driver is not optimally set-up.

But, with an external low noise VCO (what I have designed in for them) it is possible to get jitter well under 70fs with correctly set up LVPECL.   That level of jitter is degraded by less than optimal drivers, hence setting up the driver near perfectly becomes an issue.  Having the driver be voltage compressed or current compressed is just like the amplifier chain that follows a VCO--it up-converts baseband noise to the carrier that is then expressed as phase noise and jitter.  Since that noise is outside the PLL loop, it is not suppressed by the PLL.   It is purely additive noise.  This is becoming recognized in lower noise PLL design.  For example, Mini-Circuits has a new line of "Low phase noise RF amplifiers" that are intended to not degrade the phase noise of low noise PLL's.  

So, for customers seeking the lowest jitter in a clock system, there is a need to understand the output clocking to a fairly deep degree.  We cannot do that when there is no representative circuit of the output driver in different modes, no explanation of the DC biasing inherent in the datasheet and its compliance range, and no explanation of why the EVM kit schematics are ignoring the DC bias that the datasheet is recommending.  

As an example of a buffer part that shows its different phase noises in different modes, I attach a graph from the Analog LTC6957 buffer.  LVPECL is about 2dB better than LVDS on the floor and 6dB better on the close in skirt (below 10kHz offset).   But, that no doubt assumes correctly set-up LVPECL.  Get that LVPECL out of its intended region of operation, and it will almost certainly be noisier.  

Thanks, 

Farron