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Clock generation for ADC

Other Parts Discussed in Thread: ADS62P48, CDCE62002, CDCE62005, CDCE72010

Hi,

I want to generate the following sampling frequencies for the ADC ADS62P48:

            1.  fs=256/335*88.0525   MHz

            2.  fs=16/21*88.0525   MHz

Could you please suggest a clock synthesizer for generating the above mentioned divider ratios? 

Thanks

Radhika

        

  • Hello Radhika,

    to generate the sampling frequencies it is recommended to use the CDCE62002/5.

    Please find the CDCE62002 device settings for both frequencies in the attached ini files.

    http://e2e.ti.com/cfs-file.ashx/__key/CommunityServer-Discussions-Components-Files/48/5008.CDCE62002_2D00_67M088.inihttp://e2e.ti.com/cfs-file.ashx/__key/CommunityServer-Discussions-Components-Files/48/0005.CDCE62002_2D00_67M288.ini

    Best regards,

    Julian

  • Hi Radhika,

    As Julian mentioned the CDCE62002 or the CDCE62005 can generate both frequencies but not simultaneously. That means a CDCE62002 can be used to generate frequency 1 and another CDCE62002 can be used to generate frequency 2.

    In order to achieve 70dB SNR with this ADC for an fin=80.0525MHz. It would be doable to use a sampling clock of a maximum 611fs rms jitter, considering that the apperture jitter is 145fs rms, using a clock input of LVPECL levels. With 70dB SNR that NOB is 11bits.

    To achieve a higher SNR (74dB) and therefore a higher NOB 12 the sampling clock should show a maximum jitter of 369fs rms. In this case it would be recommended using additional crystal filter for the output frequency of interest plus transformer (as per picture attached)

    The CDCE72010 is recommended if the ADC sampling clock would require a better jitter performance for a higher NOB. (in this case dividers setting: outputDivider=5, M=67, N=256. This solution requires external low pass filter and an external  VCXO=305.8MHz the phase detector that updates with a frequency of 1.194MHz.).

     

    Best regards,

    MJ