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50M triangle wave to square wave,CDCS503?

robinfeng
Intellectual 960 points
Other Parts Discussed in Thread: CDCS503, LMV7219, LMH7220, LMH7322, LMH7324, DS90UR124, DS90UR241

Customer video process output clk is a triangle wave, we want reshape that to square wave, Does CDCS503 can do that or suggest other part(frequency about 50Mhz)?

  • 0
    TI__Expert 3985 points

    Hi Robin,

    what is the triangle-wave amplitude? Slew rate is in this case a key parameter.

    Thanks and best regards,

    Leandro

  • 0 in reply to Leandro_z
    TI__Mastermind 32575 points

    If slew rate is a concern, there are some high-speed comparators with internal hysteresis to ensure clean switching even with low input slew rates.  Hysteresis adjustment may also be achieved with external components. 

    LMV7219 might be a good option since it has a CMOS-compatible output, but below are a few other high-speed comparators to consider.

    • LMV7219: 2.7V to 5V comparator with Rail-to-Rail Output (CMOS/TTL levels), 7 ns prop delay
    • LMH7220: 2.7V to 12V comparator with LVDS Output, 2.9 ns prop delay, no internal hysteresis
    • LMH7322: 2.7V to 12V dual comparator with reduced-swing PECL Output (also LVDS-compatible), 700 ps prop delay, adjustable hysteresis, latch feature
    • LMH7324: 5V to 12V quad comparator with reduced-swing PECL Output (also LVDS-compatible), 700 ps prop delay, fixed internal hysteresis

    Regards,

    Alan

  • 0 in reply to Leandro_z
    TI__Intellectual 2530 points

    triangle -wave amplitude is 3V.

  • 0 in reply to Jeff Wang100039
    TI__Intellectual 2530 points

    following is the application detail:

    use DS90UR241, DS90UR124 for after market infotainment , sometime DS90UR124 unlock, video source clk output is a triangle-wave, we think re-shape clk to square-wave, that will helpful for DS90UR124 lock.

  • 0 in reply to Jeff Wang100039
    TI__Mastermind 32575 points

    If the video source clock to the Serializer is a 3V triangle wave, then its transition times will be several times higher than the nominal TCLK input transition time of 2.5 ns.  Does changing the TX clock edge select (TRFB) input pin state (L to H, or H to L) to resolve the loss of lock?

    If not, I suggest trying the LMV7219 comparator to convert the triangle wave to a square wave with 3.3V LVCMOS levels to drive the TCLK input.  It may also be good to verify that the new square wave output meets the TCLK input jitter max requirement.  If not, an external PLL may be needed to clean up the jitter on the video source clock.

    Regards,

    Alan

  • 0 in reply to Alan O
    TI__Expert 3985 points

    Hi Jeff,

    thank you for providing information about the triangle amplitude and application. The CDCS503 can accept such an input signal since it has an input hysteresis voltage of 150mV (min) which makes the device robust from the noise point of view. The driving strength of the CDCS503 generates sharp output square signal with a typical rise time 0.75ns.

    Regards,

    Leandro