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LMX2531 Serial Interface / Ftest/LD Pin

Steffen Limmer
Prodigy 20 points


Hello!

When programming the LMX 2531 by an FPGA using the serial interface, I'm facing the problem that I can't observe changes to the FoLD registers on the FTEST/LD pin (which is connected to the FPGA). Instead, I can observe a signal that looks like a throughput from the OSCin (see attached waveform). In addition, I don't get an output on Fout, but I think it should be related to the programming not working properly.

The setup is as follows:

OSCin: 12MHz (~10dBm)

PLL_CLK: 12MHz

R5 (INIT1)    0x840005
R5 (INIT2)    0x800005
R5    0x8407F5
R12    0x01048C
R9    0x000BA9
R8    0x028018
R7    0x050307
R6    0x486656
R4    0x000004
R3    0x7CA623
R2    0x568022
R1    0x204001
R0    0x2C0000

From what I see in the Datasheet (p.17), serial data timing should be fine, is it?  What value should PLL_LE have prior to the first programming of the registers? To be in accordance with the LDO power up time of 10ms, I wait for 10ms after programming R2 before I program R1, is this correct? What else could I try?

Best Regards,

Steffen

pll_serial_if_timing.pdf
  • 0
    TI__Mastermind 28021 points

    In general, it is best to have the LE low unless it is used for programming. 

    As for the 10 ms wait time, this is for the internal LDOs to power up.  The action of programming either R0 or R1 activates the VCO calibration so the idea is that when the last calibration is activated, we need to ensure that the LDO is powered up.

    If the LE pin is high, it actually puts the FoLD pin in a readback mode, that is for test purposes.  This would mean that this would interfere with this signal.  So when you observe FoLD, ensure that the LE pin is low.

    Regards,

    Dean