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FPGA Jitter cleaner recommendation

Other Parts Discussed in Thread: ADS62P42, LMK04906

Hi All,

I am planning to use the PLL clock from the Altera cyclone IV to drive a 14bit ADC (ADS62P42). But the PLL clock has around ~140ps RMS jitter. I'll need around 3ps to take advantage of the 14bit ADC. I want to be able to change the sampling rate on the fly with the FPGA (Any where from 10~40MHz) and not have to program the jitter cleaner, is this possible?

1. Is it better to have a jitter cleaner with a crystal to drive the ADC and the FPGA, or..

2. Use a jitter cleaner to clean the clock from the FPGA to drive the ADC.

3. What is the simplest chip for this application.


  • Hi Albert,

    I needed the same and used LMK04906 with Spartan6 device. While you can output clock from FPGA

    and use cleaner to clean it you need to reprogram the cleaner. It is because for low jitter you need to

    have precise VCXO (Crystek is of lowest phase noise I found). VCXOs are tunable only over some

    hundreds ppm and you need to reprogram N/R to be able to lock PLLs.

    I used FPGA to directly reprogram LMK as needed.