LMK03002C Not Producing Correct Frequency

Jody,

I am trying to get an expert on the LMK03002 to assist you with this issue.

-Alex

Thanks, Alex.

- Jody

Hi Alex,

Have you had any luck finding an expert to help with this question?

I have some additional data to add:

I looked at the reference clock and it is 10.000MHz so I don't think that's the problem.  I changed the register settings to obtain a 50MHz clock and the resulting output was 57.26MHz.  So for some reason I'm getting about a 14% error on either setting.  Any insight into what could be causing this would be appreciated.

Thanks,

Jody

Jody,

I just sent a followup email yesterday to the factory group in charge of this part. If we don't hear back from anyone today, I'll escalate. Sorry for the delay.

Hi Alex,

Any word back from the factory?  I really need to get this problem cleared up before I can approve the design for manufacture.

Thanks,

Jody

Jody,

I am still working on getting someone to take a look at this for you. I'm sorry it is taking so long.

-Alex

Hi Jody,

I suspect the RESET bit in REG_R0[31] needs to be cleared after you initially set it.  According to the datasheet, R0 should be set to '0' (default) for normal operation. 

Please modify the programming sequence as shown below and advise if this allows the PLL to lock and output the correct frequency on CLKout0.

CMD_REG_R0    = x"8000_0000"; 
CMD_REG_R0    = x"0000_0000";  // added command to clear RESET bit for normal operation
CMD_REG_R4    = x"0003_0204";
CMD_REG_R8    = x"1000_0908";
CMD_REG_R11  = x"0082_000B";
CMD_REG_R13  = x"0282_800D";
CMD_REG_R14  = x"0830_010E";
CMD_REG_R15  = x"C800_500F";

Also, are you testing the device using our EVM with the default configuration?  If you made any modification(s) or are testing on your system board, please send the schematics.

Thanks,
Alan

Hi Alan,

Thanks for the suggestion - I gave it a try but saw no difference in the output.

I have some additional information:  I set the LD output to Digital Lock Detect and the result is '0' so it is not locking properly.  I've checked the input clock and the amplitude looks good.  I used the Clock Design Tool to get the filter values and the CodeLoader tool to get the register settings.  This is a custom design - I have a PDF of the schematic page that I will download - what's the best way to send it to you?

- Jody