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LMK04000

umashanker guda
Prodigy 30 points
Other Parts Discussed in Thread: LMK04000, CDCM61001, LMK03000, CDCE62002

1.We require a 100MHz output clock frequency(LVPECL).Is it necessary to use PLL1?If not,can we power the PLL1 down and what are the parameters that are needed to be changed in order to power the PLL1 down?

2.What is meant by PLL_Mux bit?

Regards,

Uma Shanker

  • 0
    TI__Guru* 94640 points

    Hi Shanker,

    If your application is clock generation, i.e. you have a clean reference clock and want to generate a 100MHz LVPECL clock, you don't need to use dual PLL jitter cleaner like LMK04000. You could simply use clock generators, for example, LMK03000 series, CDCE62002, CDCM61001, etc.