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LMK04816B internal or external feedback

Grant Downie2
Intellectual 390 points
Other Parts Discussed in Thread: LMK04816, LMK04906, LMK00301, LMK03200

Dear Sir/Madam,

I require a total of 20x 120MHz LVDS outputs.

The reference clock must be selectable between a local oscillator or backplane clock (both same frequency 10MHz). The LMK04816B looks like it would work well as it has 3 inputs.

The 20x 120MHz LVDS output pairs must have a skew of no more that 120ps.

Q. Is it better to use internal or external feedback for device 1 (0-delay dual PLL)  and device 2 0-delay PLL2)?

Regards Grant

  • 0
    TI__Mastermind 32575 points

    Hi Grant,

    As far as syncing two LMK04xxx parts, the latency from SYNC input to VCO output is not undefined.  Per the LMK04800 datasheet: “Due to the speed of the clock distribution path (as fast as ~325 ps period) and the slow slew rate of the SYNC, the exact VCO cycle at which the SYNC is asserted or unasserted by the SYNC is undefined [not deterministic].  The timing diagrams show a sharp transition of the SYNC to clarify functionality.”

    So, the uncertainty of SYNC for two devices could be as low as +/-1 VCO cycle or 2 VCO cycles pk-pk, but possibly higher depending on the SYNC input timing/slew rate and internal SYNC prop delays. 

    For example, the output phase uncertainty between two SYNCed devices can be no better than 800 ps (excluding output skew) for 2.5 GHz VCO of LMK04816.

    You should have a better chance of meeting your skew requirements using one LMK04816 or LMK04906 clock gen (50 ps output skew) followed by two LMK00301 1:10 low-jitter/low-skew DIFF fanout buffer (120 ps part-to-part skew).  If you don't have any input-to-output phase offset requirement, then 0-delay PLL mode is not necessary since there is only one clock gen in this case.

    Regards,
    Alan

     

  • 0 in reply to Alan O
    Intellectual 390 points

    Hi Alan,

    Thank you for the reply.

    The plan is to produce 20x LVDS clocks from a 10MHz clock that has a
    pair to pair skew of less than 120ps.

    Device 1 has a 10MHz clock input.
    Device 1 produces 12x120MHz LVDS outputs.
    Device 1 has one of its outputs connected to Device 2 input.
    Device 1 operates 0-delay dual PLL mode. 150MHz VCXO.

    Device 2 operates 0-delay single PLL mode.

    Device 1 and Device 2 each provide 10x 120MHz LVDS outputs.

    The datasheet states that LVDS to LVDS skew is 30ps.

     

    Q. If Device 1 has SYNC asserted, then Device 2 has SYNC asserted will
         both Device 1 and Device 2 have 30 ps skew between outputs?

    Regards Grant

  • 0 in reply to Grant Downie2
    TI__Mastermind 32575 points

    Hi Grant,

    It is possible to achieve near zero-delay phase offset close to ~0 ps nominal by adjusting the digital delay of the feedback clock.  However, there are no part-to-part variation given for output skew or 0-delay phase offset.  Another 0-delay clock gen that does have these specs readily available is LMK03200.

    Regards,
    Alan