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Using SYSREF in LMK04826B

Nithin P
Prodigy 140 points
Other Parts Discussed in Thread: LMK04826, LMK04826BEVM, CODELOADER

Hello All,

I am using codeloader4 in order to generate a jitter free clock and the evaluation module used for this purpose is LMK04826B. Consider, I am able to generate a clock of the desired frequency with the default settings in the SYSREF and Others tab. Giving an input to the CLKin1 tab I am able to see the lock on both PLL's 1 and 2.

What I want to know now is how to improve the clock generated (with no jitter) using the SYSREF tab. If I don't change settings in the SYSREF tab (i.e., with the SYNC mode operating) and change only the digital delay, analog delay and clock divider values in CLKOuts or Distribution tab, is it sufficient? I am trying the read the chapter 5 from the manual (http://www.ti.com/lit/ds/symlink/lmk04826.pdf) but I am not able to understand completely because there are many variables which I am not able to find in the CodeLoader4 software. I want to enable SYSREF (section 5.3) and want to know its significance.

Please can anyone help to understand the functioning of this SYSREF?

Best Regards,

NP.

  • 0
    TI__Expert 7845 points

    Hi NP,

    Glad to see you are up and running with the LMK04826BEVM!

     

    To start out, SYSREF is a pulse signal used for synchronizing data converters and logic devices that comply to the JEDEC JESD204B standard. JESD204B is the current version of the standard with noteworthy features such as deterministic latency across multiple data converters and logic devices, higher bandwidth --> reduction in lane count and PCB complexity, single clock generator frequency (JESD204B devices can divide down to required freq) which allows for less crosstalk. This is a quick overview, there is much more to this standard which you can find out from www.JEDEC.org.

     

    Operation wise, you are at the right section. Section 5.3 shows you how to setup the LMK04826B properly to allow you to use the SYSREF function. You will have to jump around a little in codeloader in this setup procedure. For example at the beginning you power up SYSREF circuitry (uncheck SYSREF_PD in "SYSREF" tab), then power up digital delay circuitry (uncheck SYSREF_DDLY_PD in "CLKouts" tab), then enable sync function (check SYNC_EN in "SYSREF" tab), then do a clear on SYSREF (check then uncheck SYSREF_CLR in "SYSREF" tab). There is an example on in section 5.3.1.1 that you can use as reference as well.

     

    Please let me know if you have further question. Thanks!

     

    Regards,

     

    Brian Wang

  • 0 in reply to Brian Wang
    Prodigy 140 points

    Hello Brian Wang,

    Many thanks for your help in both the posts :)

    Best Regards,

    NP.

  • 0 in reply to Nithin P
    TI__Expert 7845 points

    You're welcome NP, hope everything goes well !

     

    Regards,

     

    Brian Wang