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CDCM61002 3.3V LVCMOS input

Gregory Zschunke
Prodigy 20 points
Other Parts Discussed in Thread: CDCM61002

I just wanted to confirm that the recommended connection for a 3.3V LVCMOS input clock is to DC-couple it.  The SCAA111 application report does not mention using a 3.3V input at all.  Why is the recommendation in the datasheet for 2.5 V LVCMOS to use AC-coupling and 3.3 V LVCMOS to use DC coupling?  Wouldn't DC coupling cover both?

  • 0
    TI__Mastermind 24205 points

    Hi Zschunke,

    The internal biasing (optimal) on the XIN pin is 1.9V. While driving this input with a DC coupled 3.3V LVCMOS signal, the reference clock input threshold is around 1.65V (3.3/2) which is pretty close to this optimal internal bias and will override it. However, with a 2.5V signal, the threshold is 1.25V which is further away from the optimal internal bias. In order to not overdrive the internal bias, it is necessary to AC couple the 2.5V LVCMOS input into CDCM61002.

    Regards

    Arvind Sridhar

  • 0
    TI__Mastermind 32575 points

    From app note SCAA111:

    "The CDCM6100x can be operated with an external LVCMOS reference input applied to the XIN pin, which has internal biasing of 1.9 V. As a result of the bias voltage, the recommended voltage swing for the LVCMOS input is 2.5 V ±30% in order to maintain low distortion and low jitter of the clock outputs from the CDCM6100x. The input duty cycle should be at least 40% to 60%, and the input slew rate should be at least 0.75 V/ns."

    For a 2.5V LVCMOS input, it should be AC coupled to insure the mid-point of the clock input (assuming ~50% duty cycle) is biased to the input bias voltage (same as input switching threshold level).  Typically, the mid-level of the clock signal is where its edge rate is highest.

    For a 3.3V LVCMOS input, AC coupling is not nessary since the 50% level (1.65V) is close enough to the input switching threshold level of 1.9V.

    Regards,
    Alan