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Locking of PLL2 in LMK04826BEVM

Other Parts Discussed in Thread: CODELOADER

Hello Brian Wang,

In my last post ( you had explained on how to achieve lock on PLL2. I have followed the steps but sometimes not able to lock on PLL2. I have attached a zip folder which has 2 files. In the first one I am able to achieve lock on both PLL's and in the second file PLL2 is not locked. Please can you check and tell me what is wrong in second file?

In both cases I am applying input to CLKIn1 port of the eval module.

Thanks and Regards,


CodeLoader4 Mac
  • NP,

    I see, I see. So if you see below block diagram of our current EVM board, PLL1 has a 122.88 MHz VCXO, so basically PLL1 output, Fout (PLL1) = Fin / R * N has to equal 122.88 MHz. In the second case you have 500 MHz set for codeloader at PLL1 output, which will not work unless you can get that from 122.88 MHz / R * N or replace that external VCXO on the board with a 500 MHz one. Please let me know if you have any other questions. Thanks!


  • Hello Brian Wang,

    Many thanks for your reply. I knew the inernal VCXO is 122.88MHz. So, I should never use any other frequency at the output of PLL1 apart from 122.88MHz?

    I was confused because I was able to get a lock on PLL1, when I had inputted 500MHz and output of PLL1 was set to 500MHz. But if I remove external VCXO then the phase noise will not be less since that is the one which has a narrowband operation and reduces the phase noise, right?

    Best Regards,


    PS : I kindly request Gabe Ayala not to verify the answer. Please give chance for the original author of the post to verify the answer. I think you are the moderator of the forum, but I kindly request you to close/verify the post after 3 days of inactivity from the author.