CDCLVP1204 / CDCLVP1212 input edge rate question

Hi Gavin,

The datasheet specificaitons for the device are guaranteed for reference clock slew rate >= 1.5V/ns. While operation with a reduced slew rate input is possible, performance specifications such as buffered output clock noise floor and random additive jitter will be degraded.

Regards

Arvind Sridhar

In the same order of things, please, taking into account this 1.5V/ns CDCLVP1204 spec, and the 3V/ns spec for LMK00304, which one would you you reccomend for minimum LVPECL output jitter with a 6V/ns differential LVPECL 10 MHz input (150ps rise/fall times)? I supposed that LMK devices were preferable as far as many specify 0.15V/ns input, but this is not the case of LMK00304, is there any other buffer/distributor (no generator/PLL) of these families with 0.15v/ns input SR specs for maximum performance?

Thanks Arvind, it is true that comparison of chips leads to think an apparent better noise figures for LMK00304, but in my opinion, as this input is to drive a PLL that uses LMK04805 device PLL1 (input CLK IN), the BW that is relevant is the DC to 1KHz, that is not included in your figures or in the jitter usual integral (10KHz to 20MHz). I wonder that both chips additive jitter in these areas will be much below the source noise. Our preference for 1204 is based on size, pincount and simplicity of circuit around, on the other hand our doubts were due to the fact that 1204 is older, and the data sheet misses for example PSRR or channel isolation data.

One can appreciate a difference in the phase noise figures at 1KHz (00304 LVPECL out fig. 21 vs. 1204 fig. 22), being there the LMK00304 apparently 3 or 4 dB better, but in both cases the dominant noise at these low frequencies is the source noise, and the sources used seem to be different (better in the LMK00304 measurements), also the 1204 signal frequency is higher so how to compare well below 1-10KHz?

Arvind, I am less sure now. than before... as far as the figure 22 of data sheet gives for CDCLVP1204 -140.3dBm/Hz at 1 KHz offset for a 156 Mhz output. Normally, the lower the frequency the better the phase noise.

So I had managed that -140.3 would be the very worst noise I can find at 1204 output for a 10 MHz frequency, and the same -153.4 at 10Khz and -157.4 at 100KHz as per fig. 22. 1KHz and 10KHz data of your table here are worst than the data sheet ones. Can I trust the data sheet? because even if the PLL1 will reject much of the >10Hz noise, it will still not remove all of it, we have detected a 1-2dB degradation at 1-10Khz with the new 1204 figures of here.

We need that all the noise induced in the 10 MHz section must be below -140dBC/Hz / 1KHz, for a 10 Mhz signal.

I wonder if it is the Wenzel oscillator who introduces more low requency noise than in the data sheet measurement.

And anyway I wonder if the 10 MHz signal noise will be much better as normally, or the behaviour of this comparator is different seing that th 100 Mhz figures you give me are worst than the 156 MHz data sheet ones...

Arvind, being solved the previous issue about a CDC1204 application i would like to ask you about another one.

We are involved in a new design of an auxiliary module managing sinc signals of 1Hz (1pps) and 10 MHz), that will be auxiliar via DPLL to the main system clock.

Both signals are in digital format LV3.3V originally single ended.

We need some functions as demultiplexer/switch (dual input/one output), mux (one input/2 or 3 outputs) and so on.

I am considering the use of the CDC1204 for the use as demux, being able to select one of two inputs.

My doubt is about the use of the chip, and in general of the LVPECL, for frequencies as low as 1Hz. The reason is that this is the frequency of the pulse but we need to have the fastest rise time as possible. the output of this system is directed to a DPLL that will geerate the system clock and so it is very important for jitter concerns not to add jitter either to the 10 Mhz and to the 1pps signals. Being the 1pps signal positive pulses once every second, but with very fast rise time, i guess that I can use these technology at leats working with signals DC coupled and limitig their swing to 3.3V, is it correct? As the duty cycle uses to be small, the only "special" thing of the signal is that it stays near one second each period at 0V.

Thanks in advance