About clock generator and jitter cleaner

g.f,

We need to be clear to discern the difference between true definitions and jargon adopted by marketing.

Here's how I would define it:

Clock Generator:

A device that can produce frequencies that do not divide into the input frequency, or in the case of no input frequency, it can generate any frequency.

In other words a buffer or divider buffer generates frequencies, but they divide into the input frequency.  If there is no input frequency (i.e. on chip crystal), then any frequency is a clock generator.

Jitter Cleaner:

A device that can produce a output frequency with better jitter than the input frequency.

So the terms are not mutually exclusive.  For instance, the LMK03806 we sell as a clock generator, but if you had a noisy clock, then at far out frequecies beyond the loop bandwidth, the PLL would actually clean up the jitter.  Application note 1734 gives an example of this with the LMK03000 series of clock generator.

http://www.ti.com/lit/an/snoa508b/snoa508b.pdf

In this case, the noise being cleaned up is at far offsets.

Likewise, if a jitter cleaner can produce a frequency that does not divide into the input frequency, then it is also a clock generator.  So the terms are not mutually exclusive.

What we typically mean when we call something a "Jitter Cleaner" is something with the ability to clean up a noisy clock at low offsets like <1 kHz.   For our products, this typically means that we have one PLL with a very narrow bandwidth and external VCXO to clean up the close in noise and then we often multiply it up to a highr frequency with the second PLL.

So for our products, by "Jitter Cleaner", we say that it has 2 PLL stages.   The one place where I would argue against how we have categorized things is the LMK02000.  In this case, we have a single PLL that uses an external VCXO, so I would call this a jitter cleaner as well. 

Anyways, hopefully this sheds some light on this.

Regards,

Dean