• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 20 subscribers
  • Views 660 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

using LMK02000 as a clock divider

Naveen Kadayinti
Prodigy 40 points
Other Parts Discussed in Thread: LMK02002, LMK02000, LMK01000

I intend to use LMK02000 to divide a 125MHz to 200MHz signal by 510. However the output oscillates with multiple tones > 50MHz, when the input frequency is below 320MHz. My supply voltage is 3.3V. I have also tried LMK02002 but the behavior is same.

Also I would like to know the expected behavior of the chip when the part is programmed but no input is applied.

My experiment setup is as follows

 1) OSCin input is not connected. 2) Fin is driven single ended with Fin* bypassed to GND with 0.1uF 3)LDO bypass and bias pins decoupled as recommended 4) ClKout4 terminated with resistors (127 ohms to VDD and 82 Ohms to GND) 5) All other pins left floating 6) Program R0 with "80 00 00 00" 7) Program R4 with "00 03 FF 04" (Or other division ratios) 8) Program R14 with "2A 00 FF 0E"

  • 0
    TI__Mastermind 32575 points

    Some questions/comments:

    • Try also programming PLL_N divider value to 1.  Perhaps the PLL_N divider output frequency is mixing with the input and output frequency, and showing up as spurious.
    • Can you share a measurement plot showing the output oscillation you describe, and include the test setup / conditions?

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 40 points

    I have programmed PLL_N as suggested, but there is no change in the circuit behaviour.

    I have attached images of the oscillation I observe.

  • 0 in reply to Alan O
    Prodigy 40 points

    I have programmed PLL_N as suggested, but there is no change in the circuit behaviour.

    I have attached images of the oscillation I observe. 

    The attachment did not get uploaded the last time.

    LMK02002.zip
  • 0 in reply to Naveen Kadayinti
    TI__Mastermind 32575 points

    Can you make sure there is some offset voltage between OSCin and OSCin*, so that there is no input "chatter" on the OSCin reference path?  If necessary, apply an offset voltage to insure the OSCin input state is static (low or high). 

    For the Fin input, can you make sure you're meeting the input slew rate requirement of 0.5 V/ns and input power range of -13 to +8 dBm?

    Could the noise be coming from the 3.3V power supply used for the DUT and output biasing network?

    Can you measure the output differentially to see if the oscillation on the output is common mode noise? 

    If you only need a clock buffer/divider, I would instead suggest LMK01000 family (similar to LMK02000 but without the PLL circuitry).

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 40 points

    Hi Alan,

    I have found the bug in my PCB. The problem was the OSCin and Fin pins were swapped, and the input was going to OSCin. Hence at high frequencies it was getting coupled to Fin and the divider was working. 

    I have shorted the OSCin and Fin pins for now and the output is as expected. 

    I have used LMK02000 instead of LMK01000 as I want to use it as a PLL in the next version of my circuit.

    Thank you very much for your time.

    Naveen