Hello,
I am using the LMK04000 to clean up a recovery clock source. However I require that the phase relationship between the input clock source and the output frequency be consistent (always the same phase difference).
I can successfully get a constant phase different between the input clock source and the output of the PLL 2 VCO divider. However, if I enable the additional clock dividers (after the VCO divider) I get a changing phase relationship between the input clock and the outputs (i.e. CLKout1). This phase relationship seems to change randomly, when the chip is reprogrammed, or when the input clock is removed and reapplied.
The part configuration is:
PLL 1:
reference oscillator = 20 MHz
phase detector frequency = 20 MHz
VCXO = 100 MHz
PLL2:
reference oscillator = 100 MHz
phase detector frequency = 100 MHz
VCO = 1200 MHz
VCO divider = 6
CLKout1 Clock divider = 10
Thanks,
