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Phase Noise Characteristics for the LMX2581EVM - Performance Widely Different From Simulation Results.

Other Parts Discussed in Thread: LMX2581, CODELOADER, LMX2581EVM

Hello,

I am using an evaluation module of the LMX2581 to generate a 2.7GHz output with the minimum possible RMS Jitter. Using CodeLoader, I have programmed LMX2581 to Integer Mode to generate an RFout of 2.7GHz by providing a 100MHz square wave as an external OSCin .  The Agilent E5052B Signal Source Analyzer is being to observe the noise performance of the generated output.

In the above scenario, the signal source analyzer shows an RMS jitter of 276.78fsec, when integrated from an offset of 10kHz to 10MHz.

However, when using the Clock Design Tool with the same Integer Mode settings and same loop filter values as that of the LMX2581EVM the simulation results show a much better RMS jitter of 120fsec for the same offset range.

What could be the reason for this large difference in simulated and experimental results? What can I do to improve the experimental results? Any help would be much appreciated.

Thanks and Regards,
Ajay

  • Hi Ajay,

    I believe the simulation tool suggests you a loop bandwidth of greater than 200kHz and with a very small value for C3. Unfortunately, in reality there is a minimum value requirement for C3. With reference to the datasheet, a 2.2nF to 3.3nF capacitor is recommended for C3. This capacitor value will limit the achievable loop bandwidth to less than 100kHz. For example, in the simulation too, you can try to design a loop with bandwidth 70kHz, Phase margin 55deg and then click the Calculate button. It shall return C3 of 0.18nF. Click the Show Advanced Info>> button and adjust the T31 Ratio (to the left) to make C3 = 2.2nF. Then the simulated jitter will be around 200fs. To do a better accurate simulation, you should provide the phase noise profile of the 100Mhz reference clock. To do this, click the Simulation button in the OSCin block and then click Enter Custom Phase Noise.

  • Hi Noel,

    Thank you for the prompt reply. 

    Does the limitation on C3 mean that one would never be able to achieve the 100 fs RMS Jitter that the datasheet for the LMX2581 claims? More so because the clocking application in section 9.2.1 of the datasheet seems to show an experimentally obtained RMS Jitter of approximately 100 fs.  

    Also, from what I understand, the C3 capacitance is recommended to avoid degradation of VCO phase noise characteristics. However, the simulation tool shows lower VCO phase noise for the case when C3 is not 3.3nF, and also better total phase noise characteristics. Why then is it recommended to have C3 ranging from 2.2nF to 3.3nF?

    Awaiting your reply,
    Ajay

  • Hi Ajay,

    The tool was not able to take care this special requirement for LMX2581, so the recommended C3 value may be very small.
    It is not very accurate to say we have special requirement to C3. The correct way to say is we have requirement on the shunt cap which is closest to the VCO. In a third order loop filter, that is C3. In a second order loop filter, that is C1.
    The design in the application example is very clever. It adopts a second order filter and try to make C1 as large as possible. As you can see from Figure 17 in section 8.3.7, the difference between 1nF and 3.3nF is not big. However, the difference between 1nF and 300pF is huge. In order to make C1 big possible, both charge pump current and phase detector frequency were set to their maximum values. Now, C1 is big enough and at the same time, loop bandwidth can be made very large. As a consequence, the phase noise is optimized, so does the jitter.
    You may consider to use this technique in your design.
  • Hi Noel,

    Thank you for the clarification. I shall try it out.

    Regards,
    Ajay