Please let me know recommended clock solution.
(Attached below)
※Jitter cleaner input are LVDS or LVPECL.
Clock generator output is LVDS.
・I think that jitter cleaner is CDCM7005, but Clock generator and Switch were not find best solution.
Best regards,
Satoshi
Hi Satoshi-San,
A 148.5 MHz or 148.5 / 1.001 MHz signal can be cleaned up using LMK04110 with a 27 MHz off-the-shelf VCXO. PLL dividers would need to be re-configured when the reference clock is switched to a new frequency. I have set the configurations for PLL1 and PLL2 on LMK04110 under both scenarios as shown below. Please note that the loop filter component values are similar between the two configurations. Only the dividers would need to be re-programmed via microwire(SPI) interface
I am not sure about the mux recommendation. Please post a thread on http://e2e.ti.com/support/logic/ and someone should be able to help you
As far as the clock generation is concerned, we do not have a single chip solution. However, two cost effective and high performance clock generators, CDCM6208 and CDCE62005 can be used to generate the required clocks. Please see attached solution block diagram.
If the image is not clear, please send an email to arvind.sridhar@ti.com
Regards
Arvind
