Dear Support team,
I wish to know how much maximum skew we could have between all DCLKoutX/Y outputs with the same format at FCLK=400Mhz.
In the datasheet SNAS605AQ –MARCH 2013–REVISED AUGUST 2014 , I could read 50ps in typical between DCLKoutX to DCLKoutY at FCLK=245Mhz
How could we reduce this delay ?
Thanks in advance
Best regards
