LMK04821 PLL2_DLD (STATUS_LD2) output abnormally and ask for help.

user4422205

Prodigy 40 points

Other Parts Discussed in Thread: LMK04821

I'm currently working on LMK04821 to generate 2GHz clock. Here are some configurations on my board.

1. PLL1 is shut down. A 20MHz CMOS clock, generating from an OCXO, goes into OSCin PIN directly.

here is the phase noise of the OCXO:

2. PLL2_DLD is configured to be connected to STATUS_LD2 internally.

here is the external loop filter configueration of PLL2:

From the FFT analysis of the DSO, the output of 2GHz clock should be locked by PLL2.

However, the output of STATUS_LD2 is an abnormal waveform instead of a constant high or low, as shown below. Does this means PLL2 is still not locked?

Thank you so much!!

PS: Detailed LMK04821 configueration code could be provided upon request.

over 10 years ago

0 user4422205 over 10 years ago

Prodigy 40 points

pictures are not displayed smoothly.

here are backups.

phase noise of OCXO:

the external loop filter configueration of PLL2:

FFT analysis of DSO:

output of STATUS_LD2:

0 Ahmed Noeman over 10 years ago in reply to user4422205

TI__Expert 3520 points

Hi,
Could you please send the complete mac configuration file. As you mentioned, the PLL seems in lock state already. so it's a DLD issue. the DLD behavior depends on several parameters like lock window, and lock cycle counter as well as hold-over mode, that should be obvious from the config file.
Regards,
Ahmed

0 user4422205 over 10 years ago in reply to Ahmed Noeman

Prodigy 40 points

here you go and thank you so much!

SYSREF_ON_init_2.rar

0 Ahmed Noeman over 10 years ago in reply to user4422205

TI__Expert 3520 points

The loop filter seems fine, even with the VCO gain range of 12 V/ns and 20 V/ns, the phase margin is always above 70 degrees. I wouldn't relate it instability.

Calculating the ppm accuracy required to achieve lock using equation 3 in datasheet, ppm = 9 ppm. I was going to suggest to relax this tight value an check the status output if it stays constant by decreasing PLL2_DLD_CNT to let's say 4096

However, The oscillation frequency of the DLD status output is a bit higher than 100 MHz. is my reading correct? if that's the case, then it can't be an artifact of the DLD circuit, as the DLD can't act that fast, it requires thousands of cycles to show lock!

I guess it's a possible analog issue related to the status output pin, please check how the status pin is connected on the board. You can try monitoring the PLL2 DLD on the other status pin if that occurs.

Kind Regards,

Ahmed

0 user4422205 over 10 years ago in reply to Ahmed Noeman

Prodigy 40 points

I've found the cause. Something wrong with the circuits connected to the STATUS_LD2 pin. It goes to high finally. Thank you so much and have a good day.

0 Ahmed Noeman over 10 years ago in reply to user4422205

TI__Expert 3520 points

Great news! was the right guess then. thanks for the update.

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LMK04821 PLL2_DLD (STATUS_LD2) output abnormally and ask for help.