issues with LMK04808 eval board

Ramakrishna Bachimanchi

Intellectual 300 points

Other Parts Discussed in Thread: LMK04808, CODELOADER

Hi,

I am trying to use LMK04808 board to configure output clock frequency

Dual loop mode ,0-delay, int vco

PLL1 input frequency 936 MHz, PLL1 vco 936 MHz

PLL2 input frequency 80 MHz VCXO, VCO 2808 MHz

when I load the registers, everything looks good. Output is set to 936 MHz and output tracks with input . Great!

if I disconnect the uWire programming cable, PLL gets into Holdover mode and the output frequency goes to ~1880 MHz. I am not sure why this happens

I am trying to program LMK04808 with the same register set with an FPGA and the result is the same(directly goes into holdover mode once all the registers are loaded from fpga). I am struggling to understand why the clock conditioner is behaving this way. it would be great, if someone can please look into this.

Thanks,

Ramakrishna

over 10 years ago

0 Julian Hagedorn over 10 years ago

TI__Mastermind 20900 points

Hello Ramakrishna,

one potential rootcause for the frequency change when you unplug the uWire programming cable could be glitches on the uWire_LE. That could load random values into the registers.
You could try to write uWire_LOCK = 1 (R31 bit5) first before unplugging the cable.

One question to the frequency plan: PLL1 VCO is 936MHz, but your VCXO is 80MHz?
You should have only one of these. In fact, if you use a 936 MHz VCO in the PLL1 loop, you are violating the max input frequency at OSCin.
If you share you codeloader mac file, i could do a cross check on the register settings.

best regards,
Julian

0 Ramakrishna Bachimanchi over 10 years ago in reply to Julian Hagedorn

Intellectual 300 points

Hi Julian,
thanks for the reply. I figured it out. SYNC signal goes low when the connector is disconnected and I made sure that by enabling and disabling the SYNC option under the programming pins. Everything works fine now. It was odd that there was no mention of pulling SYNC pin high in order for it to work. My set up is good and everything works the way I expect it to work

PLL1 OSCIN - 936 MHz, VCO - 936 MHz, dividers of 234 for phase detector frequency of 4 MHz
PLL2 VCXO - 80 MHz (doubler, R counter 40), VCO - 2808 MHz (prescaler 2, N counter 351) for the phase detector frequency of 4 MHz

and output is 936 MHz (Clock divider 3). It would be great if you can please double check about programming the SYNC pin

Thanks,
Ramakrishna

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issues with LMK04808 eval board