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LMK04133 / LMK04133EVAL operation

Other Parts Discussed in Thread: LMK04133EVAL, USB2ANY, LMK04133, CODELOADER

Hi,

We are evaluating LMK04133EVAL by using USB2ANY with reference to snlu099A. However, even if pressing 'Ctrl - L', outputs are mute.

Input:122.88MHz/CLKin0*

Output:122.88MHz/CLKout0

Mode select of code loader:122.88MHz VCXO Default

LMK04133EVAL/EVM Ver:1111-05

*write Register

R7 (INIT) 0x00000017
R0 0x01030400
R1 0x01080101
R2 0x01080102
R3 0x01080103
R4 0x01000104
R7 0x00000007
R10 0x2150000A
R11 0x00650DEB
R12 0xE078078C
R13 0x0A04000D
R14 0x0F77002E
R15 0x1C80010F

Is there a place to be confirmed something? I have attached the setting file of code loader.

Best Regards,

Kato

  • Hi,

    Allow me to notify you of the additional information.About evaluating LMK04133EVAL by using USB2ANY, when USB2ANY uWire pins directly were connected to  LMK04133(*R12,R19 and R29 were changed to 0ohm), output frequency was mute. however, After we used these resisters, R12,R19 and R29 those were  for voltage translation, output frequency was as expected. Were these registers essential for low pass filter ?

    Best Regards,

    Kato

  • R12, R19, R29 (15 kohm) were originally intended for use with R11, R18, and R28 (27 kohm) as a voltage divider network for reducing LPT port's 5V logic levels to 3.3V levels for device's uWire input pins. Because the customer is using USB2ANY which already has 3.3V logic levels, they can remove R11, R18, and R28 to eliminate the voltage divider. 15 kohm series resistors with 33 pF filter caps may have provided some low-pass filtering against spurious noise from USB2ANY which could have impacted proper uWire programming when 0 ohm series resistor values were used. Anyway, glad they are able to program the device now and get the expected output frequencies.

    Regards,
    Alan
  • Hi Alan -san,

    Thank you for the reply. Our customer is evaluating LMK04133 without USB2ANY. Then, they couldn't get the expected output frequencies.

    One of the differences USB2ANY signals and FPGA ones, FPGA LE signal  is toggled LOW to HIGH to LOW before first set R7(INIT).

    R7 (INIT) 0x00000017
    R0 0x01030400
    R1 0x01080101
    R2 0x01080102
    R3 0x01080103
    R4 0x01000104
    R7 0x00000007
    R10 0x2150000A
    R11 0x00650DEB
    R12 0xE078078C
    R13 0x0A04000D
    R14 0x0F77002E
    R15 0x1C80010F

    Is this a problem? And could we discuss offline? If it is okay, could you please send me an email.?

    Best Regards,

    Kato

  • Kato-san,

    It appears the used CodeLoader to generate/export the register settings.  

    Can you please ask them to send the CodeLoader setup file (.mac file) used to generate the register settings?  This way I can load the GUI settings and graphically see their configuration details like CLKin frequency, VCXO frequency, and output frequencies, in addition to their register settings.

    Thanks,
    Alan

  • Hi Alan -san,

    I would like to send you customer data. So, could you agree to my friendship request ?

    Best Regards,

    Kato

  • Hi,

    I'm looking forward to hearing from you.

    Regards,

    Kato

  • Discussion taken offline for customer Confidentiality.