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Clock Jitter Attenuators

Eric VanWyk1
Prodigy 30 points
Other Parts Discussed in Thread: LMK04000, LMX2582, LMK03318

Can you please recommend an appropriate clock jitter attenuation solution?  Ideally with an eval kit available...

I have a pair of LVPECL clocks that range between 20MHz and 900MHz during normal operation.  They'll remain at a given frequency for several minutes at a time.  Currently they're producing 30ish ps of jitter, I'd like to get that down below 2ps. 

I'm unclear if the LMK04000 family is appropriate given that the frequency does change during operation.

  • 0
    TI__Mastermind 28550 points

    Hello Eric,

    Hopefully the below helps a bit, but I would need more info on your noise requirements and output frequency need.  Also, I need more info on the 20 MHz to 900 MHz range.  My understanding is that is an output.  Or is it an input your are simply wanting to jitter clean, and it would be best for the device to do jitter cleaning and pass the input frequency straight through?  This latter thing could be quite tricky.  900 MHz is above the input frequency for many LMK devices.  We also have LMX devices such as LMX2582 which have two outputs with fractional PLLs.  That could be of interest to you, it's input goes to 1400 MHz.

    -

    Are those jitter measurements time domain?  Are they RMS or peak to peak?  If RMS do you know what integration range in the frequency domain your application is sensitive to jitter in?  The dual loop architecture allows for jitter cleaning with an external VCXO, which typically has good phase noise very low frequency offsets, thereby allowing jitter cleaning to low offsets, 10 Hz for example.  However if your integration range starting offset is higher, 10 kHz for example, you could achieve jitter cleaning with only a single loop.

    Guessing, is your spec is < 2 ps RMS 12 kHz to 20 MHz?  Please refer to the presentation about choosing PLL loop bandwidths in the E2E files section for additional info.

    If you want to generate 20 to 900 MHz, you can do this using a VCO frequency / integer divider.  You could do this with LMK04000 family, but it has even only divides and VCO frequencies in the 1 to 2 GHz range.  The LMK04800 family has VCO frequencies in the 2 to 3 GHz range and has even/odd dividers, but still limited to integer divides.

    With both devices, in addition to shifting frequency by changing output divider, you could also change frequency by changing your VCO operation frequency.  The PLL is an integer N.  The LMK03318/28 is a clock generator with a fractional PLL which would give you more frequency flexibility.

    73,
    Timothy