Due to the U.S. Thanksgiving holiday, please expect delayed responses during the week of 11/22.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04131 / CLK Transmission for ADS5401


I posted same question following thread.


If you have any advice from clock side, please let me know.


I received the following question from my customer.

Could you tell me input capacitance and equivalent circuit and  of CLKIN?

They are evaluating ADS5401, and the LMK04131 provides CLK by PECL.

However the CLK can not be observed when CLK is higher than 750MHz.

(It can be observed when CLK is lower frequency for example 400MHz.)

DACLK can be observed 400MHz signal on this condition.

They think that it causes by wrong impedance matching.

So they need information of title.

And please let me know information to solve this problem.

Please let me know if there is lack of information.

Best Regards,


  • Hello,

    I reviewed the other thread. How was the input probed such that no clock was seen at 750 MHz? A high performance active probe with several GHz of BW I hope.

    If there is an impedance match issue, you could probe the signal amplitude along the PCB trace. The maximum Vpp / the minimum Vpp would tell you your VSWR which should ideally be 1. But 1.2 (20 dB return loss) to 1.5 or 1.6 (~13 dB return loss) is probably more realistic.