I posted same question following thread.
If you have any advice from clock side, please let me know.
I received the following question from my customer.
Could you tell me input capacitance and equivalent circuit and of CLKIN?
However the CLK can not be observed when CLK is higher than 750MHz.
(It can be observed when CLK is lower frequency for example 400MHz.)
DACLK can be observed 400MHz signal on this condition.
They think that it causes by wrong impedance matching.
So they need information of title.
And please let me know information to solve this problem.
Please let me know if there is lack of information.