We have three LMK61E2EVM modules whose outputs have simply gone flat after programming with the CodeLoader4 software. We are using the modules hooked up to a Xilinx KC705 board, specifically the J15 and J16 SMA inputs. These are the differential REFCLK inputs to a specific GTX on the FPGA. As they are REFCLK inputs they are Hi impedance inputs, so they are not driving back out. NOTE: After reprogramming the evaluation module, we do have to power cycle the KC705 board so the GTX pll can re-lock to the new frequency.
The problem is we can reprogram the evaluation modules a few times while the whole system is powered, and the clock changes rate per the latest setup. But after a bit the evaluation module output just dies, as in flatlines on both the P and N outputs.
Has anyone seen this before? I don't know how the part could be getting fried. We have one board that is superhuman and does not die, after multiple reprograms using the exact same setup and methodology, it still runs. The difference between this board(1) and the bad ones(3) are:
Good Board:
- LMK61E259ZDER3 (oscillator)
- MSP430 USBANY = REV I
Bad Boards:
- LMK61E259ZEKT3 (oscillator)
- MSP430 USBANY = REV K
On All boards, the jumper setups are as follows:
- J2 = USB power
- J3 = USB power
- J10 = VDD pullup
- J9 = VDD pullup
- J5 = VDD pullup
- J6 = U2A connect (also have switched to VDD pullup in troubleshooting)
