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LMX2492 locking problem

Hongrun Li
Prodigy 90 points

Other Parts Discussed in Thread: LMX2492, CODELOADER

     hello，

            When I trying to use LMX2492 and a VCO MMIC to generate a fixed frequency 24GHz,it has problem like this:

           The frequency that the cursor pointed to is a fixed frequency 23.542GHz,not 24GHz,and the other frequencies bounced without regular from 23.542GHz to about 26GHz.


          Using the oscilloscope to measure the signal of terminal Vtune ,the signal is like this:

         What are the possible causes of this phenomenon?and the corresponding solutions

       Thanks！！

       Lee

  • 0
    TI__Guru** 118430 points
    Hi Li,

    Can you describe more in details your PLL configuration and register setting? Preferably, send us screen shots of TICS Pro.
  • 0 in reply to Noel Fung
    Prodigy 90 points

    Hi,Noel,

        Thank you for your reply!

        I am not using TICS Pro but TI PLLatinum Sim to simulate PLL system  My PLL configuration is like this

     

    but there are two uncertain parameters, Kvco and VCOcap in this configration,does it matter? and my register setting using codeloader4 set like this

         thaks,

          Li

  • 0 in reply to Hongrun Li
    TI__Guru** 118430 points
    Hi Li,

    Your loop bandwidth is very high, but it should work as long as the simulation environment matches with actual. You have to find out the exact Kvco and VCOcap of your VCO and simulate again. These parameters will affect the simulation very much.
    In the PLL tab of Codeloader, it looks fine but you need to confirm that the slope of your VCO is positive. That is, output frequency increases with Vtune voltage.
    The ramp calculator is not important because you are not using the ramp function.
    Please provide the Bits/Pins tab plot for review, thanks.
  • 0 in reply to Noel Fung
    Prodigy 90 points

    Hi,Noel,

       Thank you for your reply!

       My loop bandwidth sets 600kHz because the LMX2492 datasheet says that ‘Cycle slipping typically occurs when the phase detector frequency exceeds about 100x the loop bandwidth of the PLL’  in the 11th page,and my phase detector frequency is 50MHz.

        Then I will confirm Kvco and VCOcap of my VCO as soon as possible to see whether it is its impact.

        And I am sure that the slope of myVCO is positive.

        The screen shot of Bits/Pins tab is like this ,

    Please help me check if it is wrong.

    Thanks,

    Li

  • 0 in reply to Hongrun Li
    TI__Guru** 118430 points
    Hi Li,

    The configuration is fine, maybe you can try disable FRAC_DITHER, but this is not critical.
    Did you find out the Kvco and VCOcap of the VCO?
  • 0 in reply to Noel Fung
    Prodigy 90 points
    Hi,Noel,
    Thank you for your reply!
    I only know the range of the Kvco and VCOcap ,neither of them has a fixed value, I have tried some set of values,but it seems that these two parameters have no effect on this phenomenon,any suggestion?
    Thanks,

    Li
  • 0 in reply to Hongrun Li
    TI__Mastermind 28031 points

    Can you be sure that the pull is not counting a harmonic of the vco instead of ttthe fundamental frequency?   You can observe the n divider output in the MUXout pin to check

    I say this because it looked from the picture that the VCO was locking to a low frequency and the charge pump voltage looked low