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LMK02002: No output from PD

Part Number: LMK02002
Other Parts Discussed in Thread: LMK02000

Hello,

I encountered a strange problem when trying to use LMK02002 device. I wanted to monitor the output of the PD so I configured the LD port as an  analog lock detect by writing 0x05 to PLL_MUX field in R14 and observed permanent zero level.  So I changed PLL_MUX to see the inputs to the PD. When writing 0x0B I can see divided OscIn signal exactly as expected, but when writing 0x09 that should show me divided FIn signal I can see zero level (this seems to be consistent with the behavior of the analog lock detect - divided FIn signal is not entering the PD input). But in the same time I can  see the signal from FIn port divided by the value programmed in CLKout_DIV divider at any of output ports, that means for me that the FIn signal is "recognized and processed" by the device...

I tried to change the FIn frequency (my nominal value is about 200MHz) and the power level (0 to +10dBm)  with no results - I can see signal at the output port, but there is nothing at the PD input.

Has anyone encountered such behavior  or know what is wrong? I am using LMK02000 chip in similar application and there everyfing works perfect.

Thanks in advance for a reply - Lukasz

  • Hello Lukasz,

    This seems to be a strange issue. I'll see if I can't find out something by early next week for you.

    I expect this is being used on your designed PCB? Or could it be reworked onto an LMK02000 EVM?

    73,
    Timothy
  • What's your phase detector frequency? Is it > 20 MHz? Does DIV4 bit need to be set?

    73,
    Timothy
  • Can you confirm that the PLL is on frequency or out of lock? On how many boards do you see this issue?

    73,
    Timothy
  • Hello Timothy,

    Thank you for your reply.

    I am using my own PCB and, unfortunatelly, have no access to LMK02000 EVM board. But I have the other very similar PCB with LMK02000 and using this board everything works O.K.

    In my application I am using LMK02002 as a phase detector in the system to lock the frequency of the semiconductor laser into the other laser - probably not very usual application of LMK02002 byt this is in principle an ordinary PLL with a laser as a VCO. I use 20MHz quartz oscillator as a reference (connected to OSCin), dividing it down to 312.5 kHz (N=64) - this is an intended PD frequency. So I understand that DIV4 should be at its default reset value. The input to Fin is at 195.3125MHz, that after dividing by R=625 gives again 312.5 kHz. Until now my loop is out of lock - I have no output signal from PD - the level at this output is 0V.

    For me it seems as there is no signal at the PD input associated with N divider - as I wrote in my first post after configuring PLL_MUX for N divider output (PLL_MUX = 9) LD output is 0, but simultaneously I can see 195.3125MHz signal supplied to Fin at any of CLKouts divided by proper number set in CLKout_div. When I configure PLL_MUX for R divider output I can see 156.25kHz, as it should be.

    I think that I checked evry possible point in my design but could not find any mistake. I used an external signal generator to produce 195MHz signal, varying its level and frequency - the result is still the same  - no output from PD and LD configured as N divider output. I also checked the sequences that I send to LMK to program it and they look O.K. But there must be something wrong with my design.... At this momenty I have no more ideas what I could do to make it working...

  • Hello Timothy,

    I have found the answer to my problems - it was my mistake when programming R11. I used wrong value 0x0012000B instead of correct one 0x0082000B.

    As usual, the answer was simple, but difficult to spot.

    Thank you very much for your time and appologize for bothering you with my stupid mistake...

    Regards, Lukasz
  • Great to hear you issue is resolved! No worries. Have a good day.

    73,
    Timothy