Hi,
I am using CDCE62002. I am attempting to change the loop BW for a board that is already in production. My goal is to select a BW that filters jitter from a noisy reference clock (>1ps rms) but also be able to track some modulation (~1khz) on the input reference clock without causing cycle slip or similar loss of lock issues.
My current BW is 20kHz (icp=3ma, PFD = 31.25Mhz, VCO=2GHz)
My fixed constraints are:
Input clock: LVDS 250Mhz
Output clock: LVDS 250Mhz
C1 33nf
C2 1uf
R2 39
Goal BW is between 80kHz to 100kHz. When I try using the EVM software, I have been unable to find a result that meets this desired bandwidth and satisfies Gamma Optimization and T3/T1 ratio. Can you tell me if the CDCE62002 is capable of producing this BW given the fixed constraints?
Thanks,
Chris