We operate the LMK04906 clock conditioner in the Dual PLL, internal VCO, 0-Delay Mode and apply the Sync feature for adjusted CLK out phase relationships.
The PLL1 and PLL2 lock reliable (PLL1_WND_SIZE 3.7ns, DLD_CNT 16383, PLL2_WND_SIZE 3.7ns, DLD_CNT 16383: Status_LD indicates LOCKED),
PLL1 VCXO 20MHz..
The Sync feature is configured for absolute dyncamic digital delay (NO_SYNC_CLKoutx = 1, EN_SYNC = 1, SYNC_QUAL = 1) with Feedback MUX set either to
internal CLKOut3 or external Feedback to FBCLKIN (CLKOut 2 as source).
A Sync event (HW pulse or SW SYNC_POL_INV) forces deterministic output clock phase relations as expected, but the relation to the PLL1 REFCLK
varies depending on the PLL1 Charge Pump setting ?!?.
Configuring the PLL1 Charge Pump strength to 100uA or 1.6mA results in a phase difference of ~43° in relation to the PLL1 REFCLK (6ns at 20MHz output CLK)
Configuring the PLL1 Charge Pump strength to 400uA or 1.6mA results in a phase difference of ~6° in relation to the PLL1 REFCLK (0.9ns at 20MHz output CLK)
The charge pump setting influences the phase relation for both operationg modes, internal or external feedback operation.
We've verified the effect on the LMK04906BEVAL/NOPB EVM (122.88MHz VXCO) using the Default 122.88MHz CLKIn1, 122.88MHz VCXO configuration as initial starting point
and modified the configuration to Dual PLL, internal VCO, 0-Delay Mode.
Depending on the charge pump setting, the REFIN to CLKOut relationsship jumps by 16° / ~350ps (122.88MHz CLKOut) as well when switching from 100uA to 1.6mA,
a similar effect can be obeserved.
Is there an explanation for this behaviour?
My understanding, the PLL1 charge pump setting must not influence the CLKOUT phase in 0-Delay operation other than PLL1 locked/not locked.
I fear introducing a chip which behaves not understandable.
