I'm using cdcm6208v1evm-cb.
1. Use the 25MHZ crystal oscillator on the board to input the clock source, and the PLL output clock is normal.Output clock is normal, PLL lock indicator light is long.Use other clock (we in practical applications, the reference clock frequency was only 15.625 KHZ) we use 15.625 KHZ crystals for REF clock source, PLL cannot lock (PLL lock indicator light is not bright), could you tell me the REF 6208 how much is the lower limit of the input clock?On the manual
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1. When using 15.625 KHZ reference input, I in the parameter Settings interface, respectively, set to 0 to 7 to 27 M, 27 M, 24.576 M, 148.35 M, 148.5 M, 200 M;The dividers are automatically generated, but the PLL display cannot be locked.Can you provide the correct parameters for the dividers according to these requirements?In addition, 6208 is there any requirement for the occupation of input reference clocks?