Other Parts Discussed in Thread: LMX2492, CODELOADER
I'm attempting to use the hardware ramp function of the LMX2492-Q1. I am able to lock the device to a 100 MHz reference signal and produce a clean output. I can easily change the frequency by adjusting the PLL R or N dividers. I can sweep over several GHz of bandwidth by modulating the reference signal and generate a clean LFM frequency spectrum. My issue is that I am unable to produce a ramp signal using the hardware functionality in the LMX2492. I have been able to in the past using a different VCO, and have repeated the register configuration to the extent possible, but the VCO frequency range is different which leads to changes in the ramp configuration and ramp limit registers as well as the R and N divider registers. I have tried all manner of toggling the ramp_en bit, as well as writing to the N divider in an effort to start the ramp.
What are the minimum steps required to load and start a continuously looping ramp or series of ramps?
What could prevent the ramp from starting? comparators (not used), DLD (have tried POR value and recommended value),
My register settings:
# Software Reset
0x0 0x2 0x4
# PLL_R = 1
0x0 0x1A 0x0 0x1
# PLL_N = 96
0x0 0x11 0x0 0x60
# CPPOL = 0 (Positive VCO per codeloader, Negative per datasheet), CPG = 21 (2100 uA)
0x0 0x1C 0x15
# Ramp limits config from TICS Pro
0x0 0x52 0x18 0x0 0x0
0x0 0x4F 0x0 0xF 0x0
0x0 0x4C 0x0 0x0
0x0 0x46 0x9
# Comparator limits from TICS Pro
# Ramp configuration from TICS Pro
0x0 0x5C 0x4 0xC3 0x50
0x0 0x59 0x0 0x0 0x3
0x0 0x56 0xEF
# RAMP_EN = 1, RAMP_CLK = 0, RAMP_PM_EN = 0, RAMP_TRIG_A = 0
0x0 0x3A 0x1
# Enable PLL -> output locked and visible on spectrum analyzer
Thanks!