LMK03000: Jitter information of distribution path

The SYNC* pin is an asynchronous input where the external sync signal gets sampled/ synchronized in the distribution bus clock domain. Because the external sync signal may not have guaranteed timing relationship with the internal distribution bus clock, there can be up to 1 cycle variation between when outputs are released after the sync input is deasserted.

I would characterize this as "sync uncertainty" or "sync variation", not really jitter of the distribution path.

Regards,
Alan

Moreover, die temperature can affect the internal sync propagation delay timing and increase the probability see the 1 cycle of sync variation or delay.

Regards,
Alan