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TLC551: TLC551 Threshold / Timer Circuit

Part Number: TLC551
Other Parts Discussed in Thread: SN74AUC1G14


I am looking to use a TLC551 as a reset/timer type application.    Basically when the trigger input pin goes below 0.5V, i'd like the TLC551 to set its output.  Ideally it wouldn't do this for a second or two after the +1V VCC was applied to the circuit.

I did search but couldn't find many "cookbook" type examples of circuits using this chip so asking here.


  • Larry,

    You could add a resistor from VDD to RESET and a capacitor from RESET to GND to delay the RESET voltage after power up to keep OUT low for a second for two. There is a fair bit a variance in RESET voltage threshold so the timing won't be super accurate. Adding a diode preferably schottky across the resistor will help the capacitor to discharge faster at power down in case the next power up occurs soon.
  • Happy new year, Larry

    If the post above was helpful then please click answered.
    If you need more help, just reply with more information.
  • Here's a  circuit i came up with.    Do you think this will work?   Note PWR_RESET goes from 0V to 3.3V when the circuit becomes active, and I'd like 1V2_EN to go to 0V shortly thereafter.

  • Larry,

    For U1, I suggest using the SN74AUC1G14. The input voltage to this gate will be 0V and 2.27V and that is OK . If R5 and R2 are swapped then the input would be 0V and 1V (is that what you wanted?)

    I suggest a pull down resistor at U3 pin 3 (10k is good) to keep Q1 gate low when 1V0 supply is off.
    Get rid of C80 (on pin 5) as it is not needed and will delay CONT voltage on power up.
    Expected delay for 1V0 to TLC551 active (looking at its other inputs) is about 1ms. Is that what you desire?

    If 1V0 precedes PWR_RESET then 1V2_EN goes low less than 1us after PWR_RESET goes high.
    If PWR_RESET preceded 1V0 then 1V2_EN goes low is roughly 1ms after 1V0 goes high.

    If PWR_RESET goes low while 1V0 is also up, then 1V2_EN will go high.
    If 1V0 turns off while PWR_RESET is still high, then 1V2_EN will go high.