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CDCE913-Q1: Output voltage level

Ryuuichi machida
Guru 11505 points
Part Number: CDCE913-Q1

Hi,

I would like you to confirm output voltage level in following condition.

Condition :

1. input clock selection : VCXO

2. Used output : Y1

Q.

* When we set "Y1 enable" and no input to "Xin/CLK pin", then which voltage level is observed on "Y1" pin?

Best Regards,

  • 0
    TI__Expert 5370 points
    Dear Machida,

    thank you for your question. I will answer your question Monday.

    Regards, Simon.
  • 0
    TI__Expert 8865 points
    Hi Machida,
    In LVCMOS input mode, the output is not guaranteed if there is no input on the CLKin pin(can be high level or low level).
    In VCXO mode, the output should be low, but as it is in VCXO mode, very high gain amplifier is enabled (at Xin pin) any noise might get amplified as the amplifier will automatically move to the highest gain setting. I would recommend to avoid that.
    If you use VCXO mode, then why it is an issue as you will connect a Xtal on board!
    Best regards
    Puneet