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LMK61E2: Suggestion for data sheet authors

John Miles
Prodigy 90 points
Part Number: LMK61E2
Other Parts Discussed in Thread: ADC121C027

When describing the I2C timing information for a part like the LMK61E2 that has an SMBus-like timeout feature, please consider actually documenting said timeout feature. :) 

  • 0
    TI__Genius 16845 points
    Hi Jonathan,

    Thank you for the feedback on the datasheet. We're looking into how to best convey this information in our datasheets.

    The "timeout" information is not highlighted in the datasheet because the LMK61E2 will be the I2C slave device, while bus timeout is typically controlled by the host.

    The device will cancel an I2C transaction if SDA and SCL have invalid timing, but this is not considered a feature of the device.

    Kind regards,
    Lane
  • 0 in reply to Lane Boyd
    Prodigy 90 points
    Good to hear. The reason this is an issue is that people occasionally prototype their I2C masters in host software, potentially several controllers upstream of the slave. Normally this saves development time, but it does result in slow bus transactions, on the order of 100 ms in my case.

    The TI ADC121C027 was OK with that, and so was the MCP4725 DAC, but the LMK61E2 fails to ACK if the 8th bit comes through more than 60 ms after the start condition. Cost a few extra hours of R&D time that might have been saved if the data sheet had mentioned that it can't be programmed statically.

    (Of course the minimum clock rate is specified as 100 kHz, but I interpreted that as more of a 'Yes, we support operation at the minimum standard I2C speed' kind of thing, rather than 'No, our internal FSM doesn't permit static operation.')